Datasheet > AZ100LVEL32NG

AZ100LVEL32NG

更新时间： 2024-09-19 04:33:23

品牌	Logo	应用领域
AZM		/
页数	文件大小	规格书
8页	178K
描述
ECL/PECL ± 2 Divider

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技术参数
数据手册

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AZ100LVEL32NG 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.7
Base Number Matches：	1

AZ100LVEL32NG 数据手册

ARIZONA MICROTEK, INC.

AZ10LVEL32

AZ100LVEL32

ECL/PECL ÷ 2 Divider

PACKAGE AVAILABILITY

FEATURES

PACKAGE

SOIC 8 Green /

RoHS Compliant /

Lead (Pb) Free

TSSOP 8 Green /

RoHS Compliant /

Lead (Pb) Free

MLP 8 (2x2) Green

/ RoHS Compliant /

Lead (Pb) Free

PART NUMBER

MARKING NOTES

•

Operating Range of 3.0V to 5.5V

470ps Propagation Delay

3.0GHz Toggle Frequency

High Bandwidth Output Transitions

Direct Replacement for ON

Semiconductor MC10EL/LVEL32 &

MC100EL/LVEL32

AZM100G

1,2

AZ100LVEL32DG

AZ100LVEL32TG

AZ100LVEL32NG

LVEL32

AZHG

1,2

LV32

C2G

1,3

Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)

Tape & Reel.

Date code format: “Y” or “YY” for year followed by “WW” for week on

underside of part.

Date code format: “Y” for year followed by “WW” for week.

DESCRIPTION

The AZ10/100LVEL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising

edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization

of multiple LVEL32’s in a system.

The LVEL32 provides a V_BBoutput for single-ended use or a DC bias reference for AC coupling to the device.

For single-ended input applications, the V_BBreference should be connected to one side of the CLK/¯C¯L¯K¯ differential

input pair. The input signal is then fed to the other CLK/¯C¯L¯K¯ input. The V_BBpin should be used only as a bias for

the LVEL32 as its sink/source capability is limited. When used, the V_BBpin should be bypassed to ground via a

0.01μF capacitor.

NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

PIN DESCRIPTION

V_CC

RESET

FUNCTION

CLK, C¯L¯¯K Clock Inputs

CLK

V_BB

RESET

V_BB

Q, Q¯

V_CC

Asynchronous Reset

Reference Voltage Output

Data Outputs

÷2

Positive Supply

V_EE

Negative Supply

V_EE

1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541

www.azmicrotek.com

12 3 4 5 6 7 8

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