Datasheet > AZ100LVEL16VV_12

AZ100LVEL16VV_12

更新时间： 2024-09-19 12:50:19

品牌	Logo	应用领域
AZM		振荡器
页数	文件大小	规格书
9页	473K
描述
Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable

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AZ100LVEL16VV_12 数据手册

AZ100LVEL16VV

Dual Frequency PECL/ECL Oscillator

Gain Stage & Buffer with Enable

www.azmicrotek.com

FEATURES

DESCRIPTION

• Minimizes External

Components

The AZ100LVEL16VV is a specialized oscillator gain stage with two

selectable data input pairs and a high gain output buffer including an

enable. Selectable data input pairs permit switching between two different

oscillator frequencies. The Q_HG/Q¯_HGoutputs have a voltage gain several

times greater than the Q/Q¯ outputs. An enable allows continuous oscillator

operation by only controlling the Q_HG/Q¯_HGoutputs.

• High Bandwidth for ≥1GHz

• Similar Operation as

AZ100LVEL16VR except

with selectable data input

pairs

The AZ100LVEL16VV also provides a reference voltage (V_BB) with

internal biasing resistors to each input to minimize external components.

• -147 dBc/Hz Typical Noise

Floor

BLOCK DIAGRAM

APPLICATIONS

•

Dual frequency oscillators

Crystal or saw oscillators that

require minimal external

components.

PACKAGE AVAILABILITY

MLP16

•

Green/RoHS Compliant/Pb-Free

Order Number

Package

Marking

AZ100LVEL16VRL¹

MLP16

AZM+16K <Date Code>²

Tape & Reel - Add 'R1' at end of PN for 7in (1k parts), 'R2' (2.5k) for 13in

See www.azmicrotek.com for date code format

www.azmicrotek.com

+1-480-962-5881

1630 S Stapley Dr, Suite 127

Mesa, AZ 85204 USA

Request a Sample

May 2012, Rev 2.0

12 3 4 5 6 7...9

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