Datasheet > AZ100LVEL16VV

AZ100LVEL16VV

更新时间： 2024-09-19 04:33:23

品牌	Logo	应用领域
AZM		振荡器
页数	文件大小	规格书
9页	94K
描述
Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer with Enable

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数据手册

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AZ100LVEL16VV 数据手册

ARIZONA MICROTEK, INC.

AZ100LVEL16VV

Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer with Enable

FEATURES

PACKAGE AVAILABILITY

•

High Bandwidth for ≥1GHz

PACKAGE

MLP 16 (3x3) RoHS

Compliant / Lead (Pb) AZ100LVEL16VVL+

Free

PART NUMBER MARKING

NOTES

Similar Operation as AZ100EL16VR

except with selectable data input pairs

Operating Range of 3.0V to 5.5V

Minimizes External Components

Available in a 3x3mm MLP Package

S–Parameter (.s2p) and IBIS Model

Files Available on Arizona

AZM+

16K

1,2

•

DIE

AZ100LVEL16VVXP

N/A

Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape

& Reel.

Date code format: “Y” for year followed by “WW” for week.

Waffle Pack

Microtek Website

DESCRIPTION

The AZ100LVEL16VV is a specialized oscillator gain stage with two selectable data input pairs and a high gain

output buffer including an enable. The Q_HG/Q¯_HGoutputs have a voltage gain several times greater than the Q/Q¯

outputs.

The AZ100LVEL16VV provides two selectable data input pairs that permit switching between two different

oscillator frequencies. When the select pin (SEL) is LOW or open (NC) data from the D0/D¯¯0 is selected. When the

SEL pin is HIGH data from the D1/D¯¯1 is selected. Allowing continuous oscillator operation, the (EN) enable works

with either data input pair. When EN is HIGH or open (NC), input data is passed to both sets of outputs. When EN

is LOW, the Q_HG/Q¯_HGoutputs will be forced LOW/HIGH respectively, while input data will continue to be passed to

the Q/Q¯ outputs. The EN and SEL inputs can be driven with an ECL/PECL signal or a full supply swing CMOS

type logic signal.

The AZ100LVEL16VV also provides a V_BBwith a 1.5mA sink/source current. Each data input is separately

connected to V_BBwith a 470Ω internal bias resistor. Bypassing V_BBto ground with a 0.01 μF capacitor is

recommended.

Each Q/Q¯ output has a 4 mA on-chip pull-down current source. External resistors may also be used to increase

pull-down current of the Q/Q¯ to a maximum of 25mA each (includes a 4 mA on-chip current source).

NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.

1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541

www.azmicrotek.com

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与AZ100LVEL16VV相关器件

型号	品牌	获取价格	描述	数据表
AZ100LVEL16VV_12	AZM	获取价格	Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable
AZ100LVEL16VVL+	AZM	获取价格	Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer with Enable
AZ100LVEL16VVXP	AZM	获取价格	Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer with Enable
AZ100LVEL32	AZM	获取价格	ECL/PECL ÷ 2 Divider
AZ100LVEL32_11	AZM	获取价格	ECL/PECL +2 Divider
AZ100LVEL32_12	AZM	获取价格	PECL/ECL 2 Divider
AZ100LVEL32DG	AZM	获取价格	ECL/PECL ± 2 Divider
AZ100LVEL32NG	AZM	获取价格	ECL/PECL ± 2 Divider
AZ100LVEL32T	AZM	获取价格	ECL/PECL ± 2 Divider
AZ100LVEL32TG	AZM	获取价格	ECL/PECL ± 2 Divider