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AZ100LVEL16VRL PDF预览

AZ100LVEL16VRL

更新时间： 2024-09-19 03:06:55
品牌 Logo 应用领域
AZM 振荡器
页数 文件大小 规格书
13页 192K
描述
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable

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AZ100LVEL16VRL 技术参数

是否Rohs认证： 不符合生命周期：Contact Manufacturer
包装说明：QCCN, LCC16,.12SQ,20Reach Compliance Code：compliant
风险等级：5.76Is Samacsys：N
JESD-30 代码：S-XQCC-N16JESD-609代码：e0
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：CERAMIC
封装代码：QCCN封装等效代码：LCC16,.12SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER
电源：-3.3/-5,3.3/5 V认证状态：Not Qualified
子类别：Other Interface ICs表面贴装：YES
技术：ECL100K温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
Base Number Matches：1

AZ100LVEL16VRL 数据手册

 浏览型号AZ100LVEL16VRL的Datasheet PDF文件第2页浏览型号AZ100LVEL16VRL的Datasheet PDF文件第3页浏览型号AZ100LVEL16VRL的Datasheet PDF文件第4页浏览型号AZ100LVEL16VRL的Datasheet PDF文件第5页浏览型号AZ100LVEL16VRL的Datasheet PDF文件第6页浏览型号AZ100LVEL16VRL的Datasheet PDF文件第7页 
ARIZONA MICROTEK, INC.  
AZ100LVEL16VR  
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable  
FEATURES  
PACKAGE AVAILABILITY  
•
Green and RoHS Compliant /  
Lead (Pb) Free Packages Available  
Enhanced Enable Operation  
High Bandwidth for ≥1GHz  
Similar Operation as AZ100EL16VO  
Minimizes External Components  
Selectable Enable Polarity and  
Threshold (CMOS/TTL or PECL)  
Available in a MLP 16 or MLP 8  
Package  
PACKAGE  
PART NO.  
MARKING NOTES  
AZM  
•
•
•
•
•
MLP 16 (3x3)  
AZ100LVEL16VRL  
16R  
1,2  
<Date Code>  
AZM+  
MLP 16 (3x3) RoHS  
Compliant / Lead  
(Pb) Free  
MLP 8 (2x2) Green /  
RoHS Compliant /  
Lead (Pb) Free  
DIE  
AZ100LVEL16VRL+  
16R  
1,2  
<Date Code>  
R5G  
<Date Code>  
AZ100LVEL16VRNEG  
AZ100LVEL16VRX  
1,2  
3
•
•
N/A  
S–Parameter (.s2p) and IBIS Model  
Files Available on Arizona Microtek  
Website  
1
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)  
Tape & Reel.  
2
3
Date code format: “Y” for year followed by “WW” for week.  
Waffle Pack  
DESCRIPTION  
The AZ100LVEL16VR is a specialized oscillator gain stage with high gain output buffer including an enable  
function. The QHG/Q¯HG outputs have voltage gain several times greater than the Q/Q¯ outputs.  
MLP 16, 3x3 mm Package (VRL) or DIE (VRX)  
The AZ100LVEL16VR provides a selectable QHG/Q¯HG enable that allows continuous oscillator operation via  
the Q/Q¯ outputs. The enable truth table on the next page shows the operating modes. Leaving EN-SEL open (NC)  
selects PECL/ECL operation for the EN pad/pin. In this mode the QHG/Q¯HG outputs are enabled when EN is left  
open (NC) or set to a PECL/ECL low.  
Connecting EN-SEL to VCC, VEE or VBB selects CMOS operation for the EN pad/pin. When EN-SEL is tied to  
VEE, the QHG/Q¯HG outputs are disabled when EN is left open (NC). When EN-SEL is tied to VCC or VBB, the QHG/Q¯  
outputs are enabled when EN is left open.1 This default logic condition can be overridden by a ≤20kΩ resistor  
HG  
connected to the opposite supply.  
The AZ100LVEL16VR also provides a VBB and 470Ω internal bias resistors from D to VBB and D¯ to VBB. The  
VBB pin supports 1.5mA sink/source current. VBB should be bypassed to ground or VCC with a 0.01 μF capacitor.  
Outputs Q/Q¯ each have a selectable on-chip pull-down current source. See the current source truth table on the  
next page for the supported values. External resistors may also be used to increase pull-down current to a maximum  
total of 25mA for the Q/Q¯ outputs.  
Each of the QHG/Q¯HG outputs has an optional on-chip pull-down current source of 10 mA. When pad/pin VEEP is  
left open (NC), the output current sources are disabled and the QHG /Q¯HG operate as standard PECL/ECL. When VEEP  
is connected to VEE, the current sources are activated. The QHG /Q¯HG pull-down current can be decreased by using a  
resistor between VEEP and VEE.  
1This operational mode (EN-SEL to VCC or VBB) is not supported for date codes prior to 0428 (July 2004). EN-SEL to VEE is supported for all  
date codes.  
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541  
www.azmicrotek.com  
1234567...13

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