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AZ100LVEL11T PDF预览

AZ100LVEL11T

更新时间: 2024-11-08 04:33:23
品牌 Logo 应用领域
AZM /
页数 文件大小 规格书
6页 77K
描述
ECL/PECL 1:2 Differential Fanout Buffer

AZ100LVEL11T 技术参数

是否Rohs认证: 不符合生命周期:Contact Manufacturer
包装说明:,Reach Compliance Code:compliant
风险等级:5.88Base Number Matches:1

AZ100LVEL11T 数据手册

 浏览型号AZ100LVEL11T的Datasheet PDF文件第2页浏览型号AZ100LVEL11T的Datasheet PDF文件第3页浏览型号AZ100LVEL11T的Datasheet PDF文件第4页浏览型号AZ100LVEL11T的Datasheet PDF文件第5页浏览型号AZ100LVEL11T的Datasheet PDF文件第6页 
ARIZONA MICROTEK, INC.  
AZ10EL11  
AZ100EL11  
ECL/PECL 1:2 Differential Fanout Buffer  
FEATURES  
PACKAGE AVAILABILITY  
RoHS Compliant / Lead (Pb) Free  
Packages available  
265ps Propagation Delay  
5ps Skew Between Outputs  
High Bandwidth Output Transitions  
75kΩ Internal Input Pulldown Resistors  
Direct Replacement for ON  
Semiconductor MC10EL11 &  
MC100EL11  
PACKAGE  
PART NUMBER  
MARKING NOTES  
AZM10  
EL11  
SOIC 8  
AZ10EL11D  
1,2  
SOIC 8 RoHS  
Compliant / Lead  
(Pb) Free  
AZM10+  
1,2  
AZ10EL11D+  
EL11  
AZM100  
1,2  
SOIC 8  
AZ100EL11D  
AZ10EL11T  
EL11  
AZT  
EL11  
TSSOP 8  
TSSOP 8  
1,2  
AZH  
EL11  
AZ100LVEL11T  
1,2  
1
2
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)  
Tape & Reel.  
Date code format: “Y” or “YY” for year followed by “WW” for week on  
underside of part.  
DESCRIPTION  
The AZ10/100EL11 is a differential 1:2 fanout gate. The device is functionally similar to the E111 device but  
with higher performance capabilities. Having within-device skews and output transition times significantly  
improved over the E111, the EL11 is ideally suited for those applications that require the ultimate in AC  
performance.  
The differential inputs of the EL11 employ clamping circuitry to maintain stability under open input conditions.  
If the inputs are left open (pulled to VEE) the Q outputs will go LOW.  
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.  
LOGIC DIAGRAM AND PINOUT ASSIGNMENT  
1
2
3
4
8
V
Q0  
Q0  
CC  
PIN DESCRIPTION  
D
7
6
PIN  
FUNCTION  
Data Inputs  
Q0, Q¯¯0, Q1, Q¯¯1 Data Outputs  
D, D¯  
VCC  
VEE  
Positive Supply  
Negative Supply  
Q1  
Q1  
D
5
V
EE  
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541  
www.azmicrotek.com  

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