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AZ100LVE310FN PDF预览

AZ100LVE310FN

更新时间： 2024-11-08 03:20:19
品牌 Logo 应用领域
AZM 时钟驱动器
页数 文件大小 规格书
5页 72K
描述
ECL/PECL 2:8 Differential Clock Driver

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中文翻译

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AZ100LVE310FN 技术参数

是否Rohs认证： 不符合生命周期：Contact Manufacturer
包装说明：QCCJ, LDCC28,.5SQReach Compliance Code：compliant
风险等级：5.88JESD-30 代码：S-PQCC-J28
JESD-609代码：e0端子数量：28
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC28,.5SQ封装形状：SQUARE
封装形式：CHIP CARRIER电源：-3.3/-5 V
Prop。Delay @ Nom-Sup：0.85 ns认证状态：Not Qualified
子类别：Clock Drivers表面贴装：YES
技术：ECL100K温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
Base Number Matches：1

AZ100LVE310FN 数据手册

 浏览型号AZ100LVE310FN的Datasheet PDF文件第2页浏览型号AZ100LVE310FN的Datasheet PDF文件第3页浏览型号AZ100LVE310FN的Datasheet PDF文件第4页浏览型号AZ100LVE310FN的Datasheet PDF文件第5页 
ARIZONA MICROTEK, INC.  
AZ100LVE310  
ECL/PECL 2:8 Differential Clock Driver  
FEATURES  
PACKAGE AVAILABILITY  
•
•
•
•
•
•
•
Operating Range of 3.0V to 5.5V  
Low Skew  
Guaranteed Skew Spec  
Differential Design  
VBB Output  
75kΩ Internal Input Pulldown Resistors  
Direct Replacement for ON Semiconductor  
MC100LVE310 & MC100E310  
PACKAGE  
PART NUMBER  
MARKING  
AZM100LVE310  
<Date Code>  
NOTES  
PLCC 28  
AZ100LVE310FN  
1,2  
1
2
Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.  
Date code format: “YY” for year followed by “WW” for week.  
DESCRIPTION  
The AZ100LVE310 is a low skew 2:8 fanout buffer designed with clock distribution in mind. The device  
features fully differential clock paths to minimize both device and system skew. The AZ100LVE310 offers two  
selectable clock inputs allowing redundant or test clocks to be incorporated into the system clock trees.  
The AZ100LVE310 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the  
device. For single–ended input applications, the VBB reference should be connected to one side of the CLKa/CLKb  
differential input pair. The input signal is then fed to the other CLKa/CLKb input. The VBB pin should be used only  
as a bias for the AZ100LVE310 as its current sink/source capability is limited. When used, the VBB pin should be  
bypassed to ground via a 0.01μF capacitor.  
Both sides of the differential output must be terminated into 50Ω to ensure that the tight skew specification is  
met, even if only one side is used. In most applications all eight differential pairs will be used and therefore  
terminated. In the case where fewer than eight pairs are used, all output pairs on the same package side (sharing the  
same VCCO) as the pairs being used should be terminated to maintain minimum skew. Failure to do this will result in  
small degradations of propagation delay (on the order of 10–20ps) of the outputs being used; while not being  
catastrophic to most designs this will result in an increase in skew.  
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.  
VCCO  
Q0  
Q0  
Q1  
Q1  
Q2  
Q2  
25  
24  
23  
22  
21  
20  
19  
VEE  
CLK_SEL  
CLKa  
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
Q3  
Q3  
Q4  
Pinout: 28-Lead  
PLCC (top view)  
VCCO  
Q4  
VCC  
CLKa  
VBB  
2
3
Q5  
CLKb  
4
Q5  
5
6
7
8
9
10  
11  
CLKb  
NC  
VCCO  
Q7  
Q6  
Q7  
Q6  
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541  
www.azmicrotek.com  
12345

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