Datasheet > AZ100LVE310

AZ100LVE310

更新时间： 2024-09-19 03:20:19

品牌	Logo	应用领域
AZM		时钟驱动器
页数	文件大小	规格书
5页	72K
描述
ECL/PECL 2:8 Differential Clock Driver

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

AZ100LVE310 数据手册

ARIZONA MICROTEK, INC.

AZ100LVE310

ECL/PECL 2:8 Differential Clock Driver

FEATURES

PACKAGE AVAILABILITY

•

Operating Range of 3.0V to 5.5V

Low Skew

Guaranteed Skew Spec

Differential Design

V_BBOutput

75kΩ Internal Input Pulldown Resistors

Direct Replacement for ON Semiconductor

MC100LVE310 & MC100E310

PACKAGE

PART NUMBER

MARKING

AZM100LVE310

NOTES

PLCC 28

AZ100LVE310FN

1,2

Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.

Date code format: “YY” for year followed by “WW” for week.

DESCRIPTION

The AZ100LVE310 is a low skew 2:8 fanout buffer designed with clock distribution in mind. The device

features fully differential clock paths to minimize both device and system skew. The AZ100LVE310 offers two

selectable clock inputs allowing redundant or test clocks to be incorporated into the system clock trees.

The AZ100LVE310 provides a V_BBoutput for single-ended use or a DC bias reference for AC coupling to the

device. For single–ended input applications, the V_BBreference should be connected to one side of the CLKa/CLKb

differential input pair. The input signal is then fed to the other CLKa/CLKb input. The V_BBpin should be used only

as a bias for the AZ100LVE310 as its current sink/source capability is limited. When used, the V_BBpin should be

bypassed to ground via a 0.01μF capacitor.

Both sides of the differential output must be terminated into 50Ω to ensure that the tight skew specification is

met, even if only one side is used. In most applications all eight differential pairs will be used and therefore

terminated. In the case where fewer than eight pairs are used, all output pairs on the same package side (sharing the

same V_CCO) as the pairs being used should be terminated to maintain minimum skew. Failure to do this will result in

small degradations of propagation delay (on the order of 10–20ps) of the outputs being used; while not being

catastrophic to most designs this will result in an increase in skew.

NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.

V_CCO

V_EE

CLK_SEL

CLKa

Pinout: 28-Lead

PLCC (top view)

V_CCO

V_CC

CLKa

V_BB

CLKb

V_CCO

1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541

www.azmicrotek.com

12 3 4 5

中文翻译

下载PDF

与AZ100LVE310相关器件

型号	品牌	获取价格	描述	数据表
AZ100LVE310FN	AZM	获取价格	ECL/PECL 2:8 Differential Clock Driver
AZ100LVE310FNR2	ETC	获取价格	ECL/PECL 2:8 Differential Clock Driver
AZ100LVEL11	AZM	获取价格	ECL/PECL 1:2 Differential Fanout Buffer
AZ100LVEL11_12	AZM	获取价格	PECL/ECL 1:2 Differential Fanout Buffer
AZ100LVEL11D	AZM	获取价格	ECL/PECL 1:2 Differential Fanout Buffer
AZ100LVEL11D+	AZM	获取价格	ECL/PECL 1:2 Differential Fanout Buffer
AZ100LVEL11NG	AZM	获取价格	PECL/ECL 1:2 Differential Fanout Buffer
AZ100LVEL11T	AZM	获取价格	ECL/PECL 1:2 Differential Fanout Buffer
AZ100LVEL11T+	AZM	获取价格	ECL/PECL 1:2 Differential Fanout Buffer
AZ100LVEL11TG	AZM	获取价格	PECL/ECL 1:2 Differential Fanout Buffer

与AZ100LVE310相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

24
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

22
SL74HC10N：高性能三输入与非门解析
2024-09-03

97
AIC1781A 电池充电控制器深度解析
2024-09-03

88

产品中心

服务支持

精选活动

关于我们

帮助中心

AZ100LVE310

AZ100LVE310 数据手册

与AZ100LVE310相关器件

与AZ100LVE310相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AZ100LVE310

AZ100LVE310 数据手册

与AZ100LVE310相关器件

与AZ100LVE310相关文章

您还可以找

您在本页遇到什么问题？