AX88780
High-Performance Non-PCI Single-Chip
32-bit 10/100M Fast Ethernet Controller
Document No: AX88780/V1.0/10/4/05
Features
● High-performance non-PCI local bus
16/32-bit SRAM-like host interface
Support back-pressure flow control for half-duplex
operation
Support big/little endian data bus type
Large embedded SRAM for packet buffers
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Support IP/TCP/UDP checksum offloads
Support interrupt with high or low active trigger
mode
Support packet length set by software
Support optional MII interface for Ethernet PHY
and HomePNA/HomePlug PHY applications
● Support Wake-on-LAN function by following events
Detection of a change in the network link state
Receipt of a Magic Packet
32K bytes for receive buffer
8K bytes for transmit buffer
● Support optional EEPROM interface
● Support PCMCIA in 16-bit mode
● Support system reference clock from 40MHz to
100MHz
● Single-chip Fast Ethernet controller
Compatible with IEEE802.3, 802.3u standards
Integrated Fast Ethernet MAC/PHY transceiver in
one chip
● Support LED pins for various network activity
indications
Support 10Mbps and 100Mbps data rate
Support full and half duplex operations
Support 10/100Mbps N-way Auto-negotiation
operation
Support IEEE 802.3x flow control for full-duplex ● 128-pin LQFP with CMOS process, RoHS package
operation
● Integrated voltage regulator and 25MHz crystal
oscillator
● 3.3V power supply with 5V I/O tolerance
● US patent approved
Product Description
The AX88780 is a high-performance and cost-effective single-chip Fast Ethernet controller for various embedded
systems including consumer electronics and home network markets that require a higher level of network connectivity.
The AX88780 supports 16/32-bit SRAM-like host interface and integrates on-chip Fast Ethernet MAC and PHY, which
is IEEE802.3 10Base-T and IEEE802.3u 100Base-T compatible. The AX88780 supports full-duplex or half-duplex
operation at 10/100Mbps speed with auto-negotiation or manual setting. The AX88780 integrates large embedded SRAM
for packet buffers to accommodate high bandwidth applications and supports IP/TCP/UDP checksum to offload
processing loading from microprocessor/microcontroller in an embedded system.
System Block Diagram
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product
specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
Released Date: 10/4/2005
4F, NO.8, Hsin Ann Rd., Science-Based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw/
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