AX88796C
Low-Power SPI or Non-PCI Ethernet Controller
Features
Document No.: AX88796C/V1.14/04/15/11
High-performance non-PCI local bus
back-pressure flow control
Supports 8/16-bit SRAM-like host interface (US
Patent Approval), easily interfaced to most
common embedded MCUs; or 8/16-bit local CPU
interface including MCS-51 series, Renesas series
CPUs
Supports Slave-DMA to minimize CPU overhead
and burst mode read & write access for frame
reception & transmission on SRAM-like interface
for high performance applications
Supports auto-polling function
Supports 10/100Mbps N-way Auto-negotiation
operation
Advanced Power Management features
Supports dynamic power management to reduce
power dissipation during idle or light traffic period
Supports very low power Wake-On-LAN (WOL)
mode when the system enters sleep mode and waits
for network event to awake it up. The wakeup
events supported are network link state change,
receipt of a Magic Packet or a pre-programmed
Microsoft Wakeup Frame or through GPIO pin
Supports Protocol Offload (ARP & NS) for
Windows 7 Networking Power Management
Supports complete I/O pins isolation during WOL
mode or Remote Wakeup Ready mode to reduce
leakage current on non-PCI and SPI slave host
interface
Supports optional EEPROM interface to store MAC
address
Supports up to four GPIOs and two of them support
Wake-On-LAN
Supports programmable LED pins for various
network activity indications with variable voltage I/O
and programmable driving strength
Integrates voltage regulator, 25MHz crystal oscillator
and power on reset circuit on chip
Supports variable voltage I/O (1.8/2.5/3.3V) and
programmable driving strength (8/16mA)
Interrupt pin with programmable timer
High-performance SPI slave interface
Supports SPI slave interface for CPU with SPI
master. The SPI slave interface supports SPI timing
mode 0 and 3, up to 40MHz of SPI CLK, variable
voltage I/O and programmable driving strength
Supports optional Ready signal as flow control for
SPI packet RX/TX
Single-chip Fast Ethernet MAC/PHY controller
Embeds 14KB SRAM for packet buffers
Supports IPv4/IPv6 packet Checksum Offload
Engine to reduce CPU loading, including IPv4
IP/TCP/UDP/ICMP/IGMP & IPv6 TCP/UDP/ICM
Pv6 checksum generation & check
Supports VLAN match filter
Supports optional clock output (25, 50 or 100MHz)
for system use, if 25MHz crystal is present
Supports optional clock input (25MHz) from system
clock to save the 25MHz crystal cost
64-pin LQFP RoHS compliant package
Operates over 0 to +70°C or -40 to +85°C temperature
range
Integrates IEEE 802.3/802.3u standards compatible
10BASE-T/100BASE-TX (twisted pair copper
mode) Fast Ethernet MAC/PHY transceiver in one
single-chip
Supports twisted pair crossover detection and
correction (HP Auto-MDIX)
Supports full duplex operation with IEEE 802.3x
flow control and half duplex operation with
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
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ASIX ELECTRONICS CORPORATION
Release Date: 04/15/2011
4F, NO.8, Hsin Ann Rd., Hsinchu Science Park, Hsin-Chu City, Taiwan, R.O.C. 300
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw