AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
Features
Product Brief
dedicated 12KB SRAM for Ethernet packet
buffering. Support full-duplex and half-duplex
operations
Supports twisted pair crossover detection and
auto-correction (HP Auto-MDIX)
MCU
8-bit pipelined RISC, single cycle per
instruction with maximum operating
frequency of 100MHz (100 MIPS)
100% software compatible with standard
8051/80390
2 GPIO ports of 8 bits each
2 external interrupt sources with 2 priority
levels
Supports wakeup via Link-up, Magic packet,
Wakeup frame, external input pin, or UART
TCP/IP
Builds in TCP/IP accelerator in hardware to
improve network transfer throughput. Support
IP/TCP/UDP/ICMP/IGMP checksum and ARP
in hardware
Supports TCP, UDP, ICMP, IPv4, DHCP,
BOOTP, ARP, DNS, SMTP, SNTP, uPNP,
PPPoE and HTTP in software
Supports
power
management
unit,
programmable watchdog timer, and 3 16-bit
timer/counters
Debug port for connecting to In-Circuit
Emulation (ICE) adaptor
5 channels of Programmable Counter Array
(PCA)
Communication Interface
On-chip Program and Data Memory
3 UART interface (with 1 supporting 921.6Kbps
and Modem control)
Embeds 128KB (AX11001) or 512KB
(AX11005) Flash memory without bank
select, and 16KB SRAM for program code
mirroring
Supports initial Flash memory programming
via UART or ICE adaptor, the so-called In
System Programming (ISP)
1 I2C interface (master and slave mode)
SPI/Micro wire interface (3 masters or 1 slave
mode)
1 1-Wire controller interface (master mode)
10/100 Ethernet PHY interface
Supports network boot over Ethernet using BOOTP
and TFTP
Integrates on-chip 3.3V to 1.8V voltage regulator
and require single power supply of 3.3V only
Integrates on-chip oscillator and PLL. Require only
one 25MHz crystal to operate
Integrates on-chip power-on reset circuit
80-pin LQFP RoHS package
Operating temperature: 0 to +70°C or -40 to +85°C
Supports reprogrammable boot code and In
Application Programming (IAP) to update
run-time firmware or boot code through
Ethernet or UART (US Patent Approval)
Embeds 32KB SRAM for data memory
Buffer Management
Embeds DMA engine and memory arbiter.
Support
3
DMA channels for high
performance data movement needed for
network protocol stack processing
*IEEE is a registered trademark of the Institute of Electrical and
Electronic Engineers, Inc.
*All other trademarks and registered trademark are the property of
their respective holders.
On-chip 10/100M Fast Ethernet MAC and PHY
Integrates IEEE 802.3 10Base-T/100Base-TX
compatible Fast Ethernet MAC and PHY with
Product Description
The AX11001/AX11005, Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY, is a
System-on-Chip (SoC) solution which offers a high performance embedded micro controller and rich communication
peripherals for wide varieties of application which need access to the LAN or Internet. With built-in network protocol
stack, the AX11001/AX11005 provides very cost effective networking solution to enable simple, easy, and low cost
Internet connection capability for many applications such as consumer electronics, networked home appliances,
industrial equipments, security systems, remote data collection equipments, remote control, remote monitoring, and
remote management. In addition to stand-alone application, the AX11001/AX11005, with popular TCP/IP protocol
suite on-chip and built-in I2C bus or SPI bus, can be used as network co-processor to offload TCP/IP protocol
processing loading from system CPU in an embedded system.
ASIX Electronics Corporation
4F, No.8, Hsin Ann Rd.,
Hsinchu Science Park,
Released Date: 1/10/2011
TEL: +886-3-579-9500
FAX: +886-3-579-9558
http://www.asix.com.tw/
1
Hsinchu, Taiwan 30078
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