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AWT6308R_08

更新时间： 2024-11-20 06:38:47
品牌 Logo 应用领域
ANADIGICS 放大器功率放大器过程控制系统PCS
页数 文件大小 规格书
8页 388K
描述
HELP2TM PCS/CDMA 3.4V/28dBm Linear Power Amplifier Module

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AWT6308R  
HELP2TM PCS/CDMA 3.4V/28dBm  
Linear Power Amplifier Module  
Data Sheet - Rev 2.3  
FEATURES  
•
InGaP HBT Technology  
•
High Efficiency:  
40 % @ +28 dBm output  
19 % @ +16 dBm output  
A
W
•
•
•
•
•
Low Quiescent Current: 15 mA  
Low Leakage Current in Shutdown Mode: <1 µA  
Internal Voltage Regulation  
T6308R  
Optimized for a 50 Ω System  
Low Profile Miniature Surface Mount Package:  
1 mm  
•
•
CDMA 1XRTT, 1xEV-DO Compliant  
Pinout Enables Easy Phone Board Migration  
From 4 mm x 4 mm Package  
M9 Package  
8 Pin 3 mm x 3 mm x 1 mm  
Surface Mount Module  
•
RoHS-Compliant Package, 250 oC MSL-3  
APPLICATIONS  
•
CDMA/EVDO PCS-band Wireless Handsets and  
Data Devices  
PRODUCT DESCRIPTION  
The AWT6308R meets the increasing demands  
for higher efficiency and smaller footprint in CDMA  
1X handsets. The package pinout was chosen to  
enable handset manufacturers to switch from a  
4 mm x 4 mm PA module with few layout changes  
while reducing board area requirements by 44%.  
The AWT6308R uses ANADIGICS’ exclusive InGaP-  
Plus™ technology, which combines HBT and pHEMT  
devices on the same die, to enable state-of-the-art  
reliability, temperature stability, and ruggedness. The  
AWT6308R is part of ANADIGICS’ High-Efficiency-  
at-Low-Power (HELP™) family of CDMA power  
amplifiers, which deliver low quiescent currents and  
significantly greater efficiency without a costly external  
DAC or DC-DC converter. Through selectable bias  
modes, the AWT6308R achieves optimal efficiency  
across different output power levels, specifically  
at low- and mid-range power levels where the PA  
typically operates, thereby dramatically increasing  
handset talk-time and standby-time. Its built-in  
voltage regulator eliminates the need for external  
voltage regulation components. The 3 mm x 3 mm x  
1 mm surface mount package incorporates matching  
networks optimized for output power, efficiency, and  
linearity in a 50 Ω system.  
GND at slug (pad)  
1
2
3
4
8
7
V
CC  
V
BATT  
RFIN  
RFOUT  
GND  
GND  
V
MODE  
6
Bias Control  
5
V
EN  
Figure 1: Block Diagram  
10/2008  
12345678

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