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TH7841ACC-R

更新时间： 2024-01-17 12:41:49

品牌	Logo	应用领域
爱特美尔 - ATMEL		传感器图像传感器
页数	文件大小	规格书
12页	207K
描述
CCD Sensor, 1.30-2.20V, Through Hole Mount, WINDOWED, DIP-28

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技术参数
数据手册

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TH7841ACC-R 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
Reach Compliance Code：	unknown	风险等级：	5.8
Is Samacsys：	N	JESD-609代码：	e0
安装特点：	THROUGH HOLE MOUNT	最高工作温度：	70 °C
最低工作温度：		像素大小：	13X11 µm
电源：	15 V	子类别：	CCD Image Sensors
表面贴装：	NO	端子面层：	Tin/Lead (Sn/Pb)
Base Number Matches：	1

TH7841ACC-R 数据手册

Features

• Pixel Size: 11 µm x 13 µm (13 µm Pitch)

• High Data Output Rate: 20 MHz

• High Responsivity and Resolution Over a Wide Spectral Range: from Blue (400 nm) up

to Near Infrared (1,100 nm)

• Low Dark Signal and Improved Uniformity

• Low Temporal Noise and High Dynamic Range: Over 6000/1

• Ease and Flexibility of Operation:

– Only Two External Basic Drive Clocks

– Choice of Internal or External Sampling and Reset

• 28-lead DIL Package

• Available with Standard Window or Antireflective Window in the Bandwidth 450 to

750 nm

Linear CCD

Image Sensor

(2048 Pixels)

Pin Identification

Pin Number

Symbol

V_OSA

Φ_ECHA

SΦ_ECHA

Φ_RA

Designation

Video Output Signal A (Odd Channel)

A Sample-and-hold Gate Input Channel

A Internal Sampling Clock Output Channel

A External Reset Clock Input Channel

Output Amplifier Drain And Internal Logic Supply

Test Point 3

TH7841A

V_DD

TP3

TP2

Test Point 2

Test Point 1

TP1

14, 15, 28

V_SS

Substrate Bias (Ground)

V_INH

Internal Sampling Clock Inhibiting Input (Dc Bias)

Transfer Clock

Φ_P

Φ_T

V_GS

Output Gate DC Bias

Φ_RB

B External Reset Clock Output Channel

B Internal Sampling Clock Output Channel

B Sample-and-hold Gate Input Channel

Video Output Signal B (Even Channel)

Reset DC Bias

SΦ_ECHB

Φ_ECHB

V_OSB

V_DR

1, 6, 7, 8, 17, 22, 23

DNC

Do not Connect

DNC

VSS

VOSA

ΦECHA

SΦECHA

ΦRA

VDR

VOSB

ΦECHB

SΦECHB

DNC

ΦRB

VGS

DNC

VDD

TP3

ΦT

TP2

ΦP

DNC

VINH

VSS

TP1

Rev. 1998A–IMAGE–05/02

VSS

12 3 4 5 6 7...12

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