Datasheet > ATR0620-100

ATR0620-100

更新时间： 2022-11-25 11:22:16

品牌	Logo	应用领域
爱特美尔 - ATMEL		全球定位系统
页数	文件大小	规格书
15页	368K
描述
GPS BASEBAND PROCESSOR

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数据手册

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ATR0620-100 数据手册

Features

•

Utilizes the ARM7TDMI^™ARM^®Thumb^®Processor Core

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Embedded ICE (In-circuit Emulation)

128 Kbytes Internal RAM

•

Fully Programmable External Bus Interface (EBI)

– Maximum External Address Space of 64 MB

– Up to Four Chip Selects

GPS Baseband

Processor

– Software Programmable 8-/16-bit External Data Bus

16-channel GPS Correlator

•

– Accuracy: TBD

– Time to First Fix: TBD

•

8-channel Peripheral Data Controller (PDC)

8-level Priority, Individually Maskable, Vectored Interrupt Controller

– Three External Interrupts

ATR0620

Summary

•

20 Programmable I/O Lines

Three USARTs

– Two Dedicated Peripheral Data Controller (PDC) Channels per USART

Master/Slave SPI Interface

•

– Two Dedicated Peripheral Data Controller (PDC) Channels

– 8- to 16-bit Programmable Data Length

– Four External Slave Chip Selects

Programmable Watchdog Timer

•

Preliminary

Power Management Controller (PMC)

– CPU and Peripherals Can Be Deactivated Individually

Clock Manager (CLM)

•

– Geared Master Clock to Reduce Power Consumption

– Sleep State with Disabled Master Clock

PWM Controller

•

– Two PWM Signals

Real Time Clock (RTC)

– Time in GPS Format and 15-bit Fractional Part of a Second

– Programmable Interrupt

– Timer with a 8-bit Fractional Part of a Second and Parallel Load

2.3V to 3.6V or 1.8V Supply Voltage

Includes Power Supervisor

•

Battery Backup Memory

9 mm × 9 mm 100-pin BGA Package

Rev. 4574CS–GPS–05/05

12 3 4 5 6 7...15

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