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ATF22V10C-10PC PDF预览

ATF22V10C-10PC

更新时间: 2024-02-25 16:50:58
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程逻辑器件
页数 文件大小 规格书
8页 237K
描述
High Performance E2 PLD

ATF22V10C-10PC 数据手册

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Features  
Industry Standard Architecture  
Low Cost Easy-to-Use Software Tools  
High Speed Electrically Erasable Programmable Logic Devices  
5 ns Maximum Pin-to-Pin Delay  
CMOS and TTL Compatible Inputs and Outputs  
Latch Feature Holds Inputs to Previous Logic States  
Advanced Flash Technology  
Reprogrammable  
100% Tested  
High  
Performance  
E2 PLD  
High Reliability CMOS Process  
20 Year Data Retention  
100 Erase/Write Cycles  
2,000V ESD Protection  
200 mA Latchup Immunity  
Dual-in-Line and Surface Mount Packages in Standard Pinouts  
ATF22V10C  
Logic Diagram  
Pin Configurations  
Pin Name  
Function  
TSSOP Top View  
CLK  
IN  
Clock  
Logic Inputs  
CLK/IN  
IN  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
IN  
IN  
I/O  
*
Bidirectional Buffers  
No Internal Connection  
+5V Supply  
IN/PD  
IN  
IN  
IN  
VCC  
PD  
IN  
IN  
Power Down  
IN  
10  
11  
12  
IN  
ATF22V10C  
GND  
PLCC  
DIP/SOIC  
Top view  
Note:  
For PLCC, pins 1, 8, 15 and 22 can be left uncon-  
nected. For superior performance, connect VCC  
to pin 1 and ground to 8, 15, 22.  
Rev. 0735C/22V10C-D–04/98  

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