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ATF22LV10C-10PC PDF预览

ATF22LV10C-10PC

更新时间: 2024-01-25 18:07:52
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程逻辑器件
页数 文件大小 规格书
9页 244K
描述
High Performance E2 PLD

ATF22LV10C-10PC 数据手册

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Features  
3.0V to 5.5V Operating Range  
Advanced Low Voltage Electricaly Erasable Programmable Logic Device  
User Controlled Power Down Pin Option  
Pin-Controlled Standby Power (10 µA Typical)  
Well-Suited for Battery Powered Systems  
10 ns Maximum Propagation Delay  
CMOS and TTL Compatible Inputs and Outputs  
Latch Feature Hold Inputs to Previous Logic States  
Advanced Electrically Erasable Technology  
High  
Reprogrammable  
100% Tested  
Performance  
E2 PLD  
High Reliability CMOS Process  
20 Year Data Retention  
100 Erase/Write Cycles  
2,000V ESD Protection  
200 mA Latchup Immunity  
Commercial and Industrial Temperature Ranges  
Dual-in-Line and Surface Mount Packages in Standard Pinouts  
ATF22LV10C  
Block Diagram  
TSSOP Top View  
Pin Configurations  
Pin Name  
CLK  
IN  
Function  
CLK/IN  
IN  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
IN  
Clock  
2
ATF22LV10C  
IN  
3
Logic Inputs  
Bidirectional Buffers  
(3V to 5.5V) Supply  
IN/PD  
IN  
4
5
I/O  
IN  
6
IN  
7
VCC  
IN  
8
IN  
9
IN  
10  
11  
12  
Programmable  
Power Down  
PD  
IN  
GND  
(1)  
DIP/SOIC  
PLCC  
Top view  
Note: 1. For PLCC, pin 1, 8, 15, and 22 can be left unconnected. For superior  
performance, connect VCC to pin 1 and GND to 8, 15, and 22.  
Rev. 0780E/LV10C-E–05/98  

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