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A1K-L67142V-55 PDF预览

A1K-L67142V-55

更新时间: 2024-01-04 22:34:52
品牌 Logo 应用领域
爱特美尔 - ATMEL ATM异步传输模式静态存储器内存集成电路
页数 文件大小 规格书
14页 178K
描述
Dual-Port SRAM, 2KX8, 55ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48

A1K-L67142V-55 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:48
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:55 nsJESD-30 代码:R-GDIP-T48
内存密度:16384 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8功能数量:1
端子数量:48字数:2048 words
字数代码:2000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-40 °C
组织:2KX8封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:5.71 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:AUTOMOTIVE
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:15.24 mm
Base Number Matches:1

A1K-L67142V-55 数据手册

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L67132/L67142  
2 K × 8 CMOS Dual Port RAM 3.3 Volt  
Introduction  
The L67132/67142 are very low power CMOS dual port Using an array of eight transistors (8T) memory cell and  
static RAMs organized as 2048 × 8. They are designed to fabricated with the state of the art 1.0 µm lithography  
be used as a stand-alone 8 bit dual port RAM or as a named SCMOS, the L67132/67142 combine an  
combination MASTER/SLAVE dual port for 16 bits or extremely low standby supply current (typ = 1.0 µA) with  
more width systems. The MHS MASTER/SLAVE dual a fast access time at 45 ns over the full temperature range.  
port approach in memory system applications results in All versions offer battery backup data retention capability  
full speed, error free operation without the need for with a typical power consumption at less than 5 µW.  
additional discrete logic.  
For military/space applications that demand superior  
Master and slave devices provide two independent ports  
with separate control, address and I/O pins that permit  
independent, asynchronous access for reads and writes to  
any location in the memory. An automatic power down  
feature controlled by CS permits the onchip circuitry of  
each port in order to enter a very low stand by power  
mode.  
levels of performance and reliability the L67132/67142  
is processed according to the methods of the latest  
revision of the MIL STD 883 (class B or S) and/or ESA  
SCC 9000.  
Features  
D Single 3.3 V ± 0.3 volt power supply  
D Fast access time  
D On chip arbitration logic  
D BUSY output flag on master  
D BUSY input flag on slave  
D Fully asynchronous operation from either port  
D Battery backup operation :  
2 V data retention  
45(*) ns to 70 ns  
D 67132L/67142L low power  
67132V/67142V very low power  
D Expandable data bus to 16 bits or more using master/slave  
devices when using more than one device  
(*) Preliminary  
MATRA MHS  
1
Rev. D (19 Fev. 97)  

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