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90USB1286-16MU PDF预览

90USB1286-16MU

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器
页数 文件大小 规格书
434页 3172K
描述
Microcontroller with 64/128K Bytes of ISP Flash and USB Controller

90USB1286-16MU 数据手册

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Features  
High Performance, Low Power AVR® 8-Bit Microcontroller  
Advanced RISC Architecture  
– 135 Powerful Instructions – Most Single Clock Cycle Execution  
– 32 x 8 General Purpose Working Registers  
– Fully Static Operation  
– Up to 16 MIPS Throughput at 16 MHz  
– On-Chip 2-cycle Multiplier  
Non-volatile Program and Data Memories  
8-bit  
– 64/128K Bytes of In-System Self-Programmable Flash  
• Endurance: 100,000 Write/Erase Cycles  
Microcontroller  
with  
64/128K Bytes  
of ISP Flash  
and USB  
– Optional Boot Code Section with Independent Lock Bits  
• In-System Programming by On-chip Boot Program hardware activated after  
reset  
• True Read-While-Write Operation  
– 2K/4K (64K/128K Flash version) Bytes EEPROM  
• Endurance: 100,000 Write/Erase Cycles  
– 4K/8K (64K/128K Flash version) Bytes Internal SRAM  
– Up to 64K Bytes Optional External Memory Space  
– Programming Lock for Software Security  
Controller  
JTAG (IEEE std. 1149.1 compliant) Interface  
– Boundary-scan Capabilities According to the JTAG Standard  
– Extensive On-chip Debug Support  
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface  
USB 2.0 Full-speed/Low-speed Device and On-The-Go Module  
– Complies fully with:  
AT90USB646  
AT90USB647  
AT90USB1286  
AT90USB1287  
– Universal Serial Bus Specification REV 2.0  
– On-The-Go Supplement to the USB 2.0 Specification Rev 1.0  
– Supports data transfer rates up to 12 Mbit/s and 1.5 Mbit/s  
USB Full-speed/Low Speed Device Module with Interrupt on Transfer Completion  
– Endpoint 0 for Control Transfers : up to 64-bytes  
– 6 Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or  
Isochronous Transfers  
Preliminary  
– Configurable Endpoints size up to 256 bytes in double bank mode  
– Fully independant 832 bytes USB DPRAM for endpoint memory allocation  
– Suspend/Resume Interrupts  
– Power-on Reset and USB Bus Reset  
– 48 MHz PLL for Full-speed Bus Operation  
– USB Bus Disconnection on Microcontroller Request  
USB OTG:  
– Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)  
for OTG dual-role devices  
– Provide Status and control signals for software implementation of HNP and SRP  
– Provides programmable times required for HNP and SRP  
Peripheral Features  
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode  
– Two16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode  
– Real Time Counter with Separate Oscillator  
– Two 8-bit PWM Channels  

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