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89C51CC01U-RLTUM PDF预览

89C51CC01U-RLTUM

更新时间: 2023-01-03 07:44:14
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器
页数 文件大小 规格书
167页 1554K
描述
Microcontroller, 8-Bit, FLASH, 40MHz, CMOS, PQFP44, VQFP-44

89C51CC01U-RLTUM 数据手册

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Features  
80C51 Core Architecture  
256 Bytes of On-chip RAM  
1K Bytes of On-chip XRAM  
32K Bytes of On-chip Flash Memory  
– Data Retention: 10 Years at 85°C  
Erase/Write Cycle: 100K  
Boot Code Section with Independent Lock Bits  
2K Bytes of On-chip Flash for Bootloader  
In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability  
2K Bytes of On-chip EEPROM  
Enhanced 8-bit  
Microcontroller  
with CAN  
Erase/Write Cycle: 100K  
14-sources 4-level Interrupts  
Three 16-bit Timers/Counters  
Full Duplex UART Compatible 80C51  
Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz)  
Five Ports: 32 + 2 Digital I/O Lines  
Controller and  
Flash Memory  
Five-channel 16-bit PCA with:  
– PWM (8-bit)  
– High-speed Output  
– Timer and Edge Capture  
Double Data Pointer  
21-bit Watchdog Timer (7 Programmable Bits)  
A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs  
Full CAN Controller:  
T89C51CC01  
AT89C51CC01  
– Fully Compliant with CAN Rev2.0A and 2.0B  
– Optimized Structure for Communication Management (Via SFR)  
– 15 Independent Message Objects:  
Each Message Object Programmable on Transmission or Reception  
Individual Tag and Mask Filters up to 29-bit Identifier/Channel  
8-byte Cyclic Data Register (FIFO)/Message Object  
16-bit Status and Control Register/Message Object  
16-bit Time-Stamping Register/Message Object  
CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message  
Object  
Access to Message Object Control and Data Registers Via SFR  
Programmable Reception Buffer Length Up To 15 Message Objects  
Priority Management of Reception of Hits on Several Message Objects at the  
Same Time (Basic CAN Feature)  
Priority Management for Transmission  
Message Object Overrun Interrupt  
– Supports:  
Time Triggered Communication  
Autobaud and Listening Mode  
Programmable Automatic Reply Mode  
– 1-Mbit/s Maximum Transfer Rate at 8 MHz (1) Crystal Frequency in X2 Mode  
– Readable Error Counters  
– Programmable Link to On-chip Timer for Time Stamping and Network  
Synchronization  
– Independent Baud Rate Prescaler  
– Data, Remote, Error and Overload Frame Handling  
On-chip Emulation Logic (Enhanced Hook System)  
Power Saving Modes:  
– Idle Mode  
– Power-down Mode  
Rev. 4129N–CAN–03/08  
1.  
At BRP = 1 sampling point will be fixed.  
1

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