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5962-9760807QYA PDF预览

5962-9760807QYA

更新时间: 2024-02-14 16:40:44
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟ATM异步传输模式外围集成电路
页数 文件大小 规格书
44页 445K
描述
RISC Microprocessor, 32-Bit, 233MHz, CMOS, CPGA255, CERAMIC, PGA-255

5962-9760807QYA 技术参数

生命周期:Obsolete零件包装代码:PGA
包装说明:SPGA,针数:255
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.31.00.01风险等级:5.46
地址总线宽度:32位大小:32
边界扫描:YES最大时钟频率:75 MHz
外部数据总线宽度:64格式:FLOATING POINT
集成缓存:YESJESD-30 代码:S-CPGA-P255
JESD-609代码:e0长度:21 mm
低功率模式:YES端子数量:255
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:SPGA
封装形状:SQUARE封装形式:GRID ARRAY, SHRINK PITCH
认证状态:Not Qualified筛选级别:MIL-PRF-38535 Class Q
座面最大高度:3.84 mm速度:233 MHz
最大供电电压:2.625 V最小供电电压:2.375 V
标称供电电压:2.5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:TIN LEAD端子形式:PIN/PEG
端子节距:1.27 mm端子位置:PERPENDICULAR
宽度:21 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

5962-9760807QYA 数据手册

 浏览型号5962-9760807QYA的Datasheet PDF文件第2页浏览型号5962-9760807QYA的Datasheet PDF文件第3页浏览型号5962-9760807QYA的Datasheet PDF文件第4页浏览型号5962-9760807QYA的Datasheet PDF文件第5页浏览型号5962-9760807QYA的Datasheet PDF文件第6页浏览型号5962-9760807QYA的Datasheet PDF文件第7页 
Features  
7.4 SPECint95, 6.1 SPECfp95 at 300 MHz (estimated)  
Superscalar (3 instructions per clock peak)  
Dual 16 KB Caches  
Selectable Bus Clock  
32-bit Compatibility PowerPC Implementation  
On-chip Debug Support  
PD typical = 3.5 Watts (266 MHz), Full Operating Conditions  
Nap, Doze and Sleep Modes for Power Savings  
Branch Folding  
64-bit Data Bus (32-bit Data Bus Option)  
4-Gbytes Direct Addressing Range  
Pipelined Single/Double Precision Float Unit  
IEEE 754 Compatible FPU  
IEEE P 1149-1 Test Mode (JTAG/C0P)  
fINT max = 300 MHz  
PowerPC  
603e™ RISC  
Microprocessor  
Family  
fBUS max = 75 MHz  
Compatible CMOS Input/TTL Output  
PID7t-603e  
Specification  
Screening/Quality/Packaging  
This product is manufactured in full compliance with:  
CI-CGA 255: MIL-STD-883 class Q or According to ATMEL-Grenoble standards  
CBGA 255: Upscreenings based upon ATMEL-Grenoble standards  
TSPC603R  
Full Military Temperature Range (Tc = -55°C, Tc= +125°C)  
IndustriaL Temperature Range (Tc = -40°C, Tc= +110°C)  
Internal/IO Power Supply = 2.5 5% // 3.3V 5%  
255-lead CBGA Package and 255-lead CBGA with SCI (CI-CGA) Package  
Description  
The PID7t-603e implementation of PowerPC 603e (after named 603r) is a low-power  
implementation of reduced instruction set computer (RISC) microprocessors Pow-  
erPC family. The 603r implements 32-bit effective addresses, integer data types of 8,  
16 and 32 bits, and floating-point data types of 32 and 64 bits.  
The 603r is a low-power 2.5/3.3-volt design and provides four software controllable  
power-saving modes.  
The 603r is a superscalar processor capable of issuing and retiring as many as three  
instructions per clock. Instructions can execute out of order for increased perfor-  
mance; however, the 603r makes completion appear sequential. The 603r integrates  
five execution units and is able to execute five instructions in parallel.  
The 603r provides independent on-chip, 16-Kbyte, four-way set-associative, physically  
addressed caches for instructions and data and on-chip instruction and data Memory  
Management Units (MMUs). The MMUs contain 64-entry, two-way set-associative,  
data and instruction translation look aside buffers that provide support for  
demand-paged virtual memory address translation and variable-sized block  
translation.  
The 603r has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603r  
interface protocol allows multiple masters to complete for system resources through a  
central external arbiter. The 603r supports single-beat and burst data transfers for  
memory accesses, and supports memory-mapped I/O.  
Rev. 2125A–HIREL–04/02  

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