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5962-87539053X PDF预览

5962-87539053X

更新时间: 2024-02-15 06:40:45
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟ATM异步传输模式输入元件可编程逻辑
页数 文件大小 规格书
13页 531K
描述
UV PLD, 15ns, CMOS, CQCC28, WINDOWED, CERAMIC, LCC-28

5962-87539053X 技术参数

生命周期:Transferred包装说明:WQCCN,
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01风险等级:5.26
Is Samacsys:N最大时钟频率:50 MHz
JESD-30 代码:S-CQCC-N28长度:11.4554 mm
专用输入次数:11I/O 线路数量:10
端子数量:28最高工作温度:125 °C
最低工作温度:-55 °C组织:11 DEDICATED INPUTS, 10 I/O
输出函数:MACROCELL封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:WQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, WINDOW可编程逻辑类型:UV PLD
传播延迟:15 ns认证状态:Not Qualified
座面最大高度:2.79 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
宽度:11.4554 mmBase Number Matches:1

5962-87539053X 数据手册

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AT22V10/L  
Features  
High Speed Programmable Logic Device  
15 ns Max Propagation Delay  
5 V ±10% Operation  
Low Power CMOS Operation  
Speed  
Temp  
"L"  
Com./Mil. Com./Mil. Others  
12/15 90/100 55  
-15,-20  
All  
I (mA)  
CC  
CMOS and TTL Compatible Inputs and Outputs  
10 µA Leakage Maximum  
High Speed  
Reprogrammable - Tested 100% for Programmability  
High Reliability CMOS Technology  
2000 V ESD Protection  
200 mA Latchup Immunity  
Full Military, Commercial and Industrial Temperature Ranges  
Dual-In-Line and Surface Mount Packages  
UV Erasable  
Programmable  
Logic Device  
Logic Diagram  
Description  
The AT22V10 and AT22V10L are CMOS high performance EPROM-based Program-  
mable Logic Devices (PLDs). Speeds down to 15 ns and power dissipation as low as  
12 mA are offered. All speed ranges are specified over the full 5 V ±10% range. All  
pins offer a low ±10 µA leakage.  
The AT22V10L provides the optimum low power CMOS PLD solution, with low DC  
power (8 mA typical) and full CMOS output levels. The AT22V10L significantly re-  
duces total system power and enhances system reliability.  
Full CMOS output levels help reduce power in many other system components.  
The AT22V10 and AT22V10L incorporate a variable product term architecture. Each  
output is allocated from eight to 16 product terms, which allows highly complex logic  
functions to be realized.  
DIP/SOIC  
PLCC  
Pin Configurations  
Pin Name  
Function  
CLK/IN  
IN  
Clock and Logic Input  
Logic Inputs  
I/O  
Bidirectional Buffers  
No Internal Connection  
+5 V Supply  
*
VCC  
0023C  
1-97  

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