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5962-02A0201VXX PDF预览

5962-02A0201VXX

更新时间: 2024-01-29 23:35:46
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输时钟
页数 文件大小 规格书
67页 1014K
描述
Serial I/O Controller, 3 Channel(s), 25MBps, CMOS, PQFP100, CERAMIC, MQFP-100

5962-02A0201VXX 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:QFF,针数:100
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.72地址总线宽度:
边界扫描:YES最大时钟频率:5 MHz
最大数据传输速率:25 MBps外部数据总线宽度:16
JESD-30 代码:S-PQFP-F100长度:19.05 mm
低功率模式:NO串行 I/O 数:3
端子数量:100最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFF封装形状:SQUARE
封装形式:FLATPACK认证状态:Not Qualified
座面最大高度:2.67 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子节距:0.635 mm端子位置:QUAD
宽度:19.05 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches:1

5962-02A0201VXX 数据手册

 浏览型号5962-02A0201VXX的Datasheet PDF文件第2页浏览型号5962-02A0201VXX的Datasheet PDF文件第3页浏览型号5962-02A0201VXX的Datasheet PDF文件第4页浏览型号5962-02A0201VXX的Datasheet PDF文件第5页浏览型号5962-02A0201VXX的Datasheet PDF文件第6页浏览型号5962-02A0201VXX的Datasheet PDF文件第7页 
TS80C51U2  
TS83C51U2  
TS87C51U2  
Double UART 8-bit CMOS Microcontroller  
1. Description  
TS80C51U2 is high performance CMOS ROM, OTP The fully static design of the TS80C51U2 allows to  
and EPROM versions of the 80C51 CMOS single chip reduce system power consumption by bringing the clock  
8-bit microcontroller.  
frequency down to any value, even DC, without loss of  
data.  
The TS80C51U2 retains all features of the 80C51 with  
extended ROM/EPROM capacity (16 Kbytes), 256 bytes The TS80C51U2 has 2 software-selectable modes of  
reduced activity for further reduction in power  
consumption. In the idle mode the CPU is frozen while  
the timers, the serial port and the interrupt system are still  
operating. In the power-down mode the RAM is saved  
and all other functions are inoperative.  
of internal RAM, a 7-source , 4-level interrupt system,  
an on-chip oscilator and three timer/counters.  
In addition, the TS80C51U2 has a second UART,  
enhanced functions on both UART, enhanced timer 2,  
a hardware watchdog timer, a dual data pointer, a baud  
rate generator and a X2 speed improvement mechanism.  
2. Features  
80C52 Compatible  
Asynchronous port reset  
Interrupt Structure with  
8051 pin and instruction compatible  
Four 8-bit I/O ports  
7 Interrupt sources  
4 level priority interrupt system  
Three 16-bit timer/counters  
256 bytes scratchpad RAM  
Full duplex Enhanced UARTs  
Framing error detection  
High-Speed Architecture  
Automatic address recognition  
40 MHz @ 5V, 30MHz @ 3V  
Low EMI (inhibit ALE)  
Power Control modes  
X2 Speed Improvement capability (6 clocks/  
machine cycle)  
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to  
60 MHz @ 5V, 40 MHz @ 3V)  
Idle mode  
Power-down mode  
Power-off Flag  
Second UART  
Baud Rate Generator  
Dual Data Pointer  
Once mode (On-chip Emulation)  
Power supply: 4.5-5.5V, 2.7-5.5V  
On-chip ROM/EPROM (16K-bytes)  
Temperature ranges: Commercial (0 to 70oC) and  
Programmable Clock Out and Up/Down Timer/  
Industrial (-40 to 85oC)  
Counter 2  
Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44  
Hardware Watchdog Timer (One-time enabled with  
(window), CDIL40 (window)  
Reset-Out)  
3. The second UART  
In this document, UART_0 will make reference to the The second UART (UART_1) can be seen as an alternate  
first UART (present in all Atmel Wireless function of Port 1 (P1.2 or P1.6 for RXD1 and P1.3 or  
&
Microcontrollers C51 derivatives) and UART_1 will P1.7 for TXD1) or can be connected to (pin6 or pin12)  
make reference to the second UART, only present in and (pin28 or pin34) of 44-pin package (see Pin  
the TS80C51U2 part.  
Rev. D - 15 January, 2001  
1

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