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5962-0054001QXC PDF预览

5962-0054001QXC

更新时间: 2024-02-06 23:17:05
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器和处理器外围集成电路微处理器异步传输模式ATM时钟
页数 文件大小 规格书
42页 2675K
描述
Rad-Hard 32-bit SPARC Embedded Processor

5962-0054001QXC 技术参数

生命周期:Active零件包装代码:QFP
包装说明:QFF,针数:256
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.31.00.01风险等级:5.71
Is Samacsys:N地址总线宽度:32
位大小:32边界扫描:YES
最大时钟频率:25 MHz外部数据总线宽度:32
格式:FLOATING POINT集成缓存:NO
JESD-30 代码:S-CQFP-F256JESD-609代码:e4
长度:37.085 mm低功率模式:NO
端子数量:256最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QFF封装形状:SQUARE
封装形式:FLATPACK认证状态:Qualified
筛选级别:MIL-PRF-38535 Class V座面最大高度:3.18 mm
速度:25 MHz最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:GOLD
端子形式:FLAT端子节距:0.508 mm
端子位置:QUAD宽度:37.085 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR, RISCBase Number Matches:1

5962-0054001QXC 数据手册

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Features  
Integer Unit Based on SPARC V7 High-performance RISC Architecture  
Optimized Integrated 32/64-bit Floating-point Unit  
On-chip Peripherals  
– EDAC and Parity Generator and Checker  
– Memory Interface  
Chip Select Generator  
Waitstate Generation  
Memory Protection  
– DMA Arbiter  
– Timers  
Rad-Hard 32-bit  
SPARC  
Embedded  
Processor  
General Purpose Timer (GPT)  
Real-time Clock Timer (RTCT)  
Watchdog Timer (WDT)  
– Interrupt Controller with 5 External Inputs  
– General Purpose Interface (GPI)  
– Dual UART  
Speed Optimized Code RAM Interface  
8- or 40-bit boot-PROM (Flash) Interface  
IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes  
Fully Static Design  
Performance: 20 MIPs/5 MFlops (Double Precision) at SYSCLK = 25 MHz  
Core Consumption: 1.0W Typ. at 20 MIPs/0.7W typ. at 10 MIPs  
Operating Range: 4.5V to 5.5V(1) -55°C to +125°C  
Tested up to Total Dose of 300 KRADs (Si) according to MIL STD 883 Method 1019  
SEU Event Rate Better than 3 E-8 Error/Component/Day (Worst Case)  
No Single Event Latch-up below an LET Threshold of 80 MeV/mg/cm2  
Quality Grades: ESCC with 9512/003 and QML-Q or V with 5962-00540  
Package: 256 MQFPF; Bare Die  
TSC695F  
Note:  
1. For 3.3V capability see the TSC695FL datasheet on the Atmel site.  
Description  
The TSC695F (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit  
RISC embedded processor implementing the SPARC architecture V7 specification. It  
has been developed with the support of the ESA (European Space Agency), and  
offers a full development environment for embedded space applications.  
The processor is manufactured using the Atmel 0.5 µm radiation tolerant (300  
KRADs (Si)) CMOS enhanced process (RTP). It has been specially designed for  
space, as it has on-chip concurrent transient and permanent error detection.  
The TSC695F includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a  
Memory Controller and a DMA arbiter. For real-time applications, the TSC695F offers  
a high security watchdog, two timers, an interrupt controller, parallel and serial inter-  
faces. Fault tolerance is supported using parity on internal/external buses and an  
EDAC on the external data bus. The design is highly testable with the support of an  
On-Chip Debugger (OCD), and a boundary scan through JTAG interface.  
Rev. 4118J–AERO–08/04  

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