Features
• Low-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
• Internally Organized 131,072 x 8
• 2-wire Serial Interface
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• Bi-directional Data Transfer Protocol
• 400 kHz (2.7V) and 1 MHz (5V) Clock Rate
• Write Protect Pin for Hardware and Software Data Protection
• 256-byte Page Write Mode (Partial Page Writes Allowed)
• Random and Sequential Read Modes
• Self-timed Write Cycle (5 ms Typical)
• High Reliability
2-wire Serial
EEPROM
– Endurance: 100,000 Write Cycles/Page
– Data Retention: 40 Years
• 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead LAP and 8-ball dBGATM Packages
1M (131,072 x 8)
Description
AT24C1024
The AT24C1024 provides 1,048,576 bits of serial electrically erasable and program-
mable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The
device’s cascadable feature allows up to 2 devices to share a common 2-wire bus. The
device is optimized for use in many industrial and commercial applications where low-
power and low-voltage operation are essential. The devices are available in space-
saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead Leadless Array (LAP) and 8-ball dBGA
packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) versions.
8-lead PDIP
Pin Configurations
NC
A1
1
2
3
4
8
7
6
5
VCC
WP
Pin Name
Function
NC
SCL
SDA
A1
Address Input
Serial Data
GND
SDA
SCL
WP
Serial Clock Input
Write Protect
No Connect
8-lead Leadless Array
NC
VCC 8
WP 7
1 NC
2 A1
SCL 6
SDA 5
3 NC
4 GND
Bottom View
8-ball dBGA
8-lead SOIC
NC
A1
1
2
3
4
8
7
6
5
VCC
WP
NC
SCL
SDA
8
7
6
5
1
2
3
4
NC
A1
VCC
WP
GND
NC
GND
SCL
SDA
Rev. 1471H–SEEPR–03/03
Bottom View
1