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ATF750LVC-15XC PDF预览

ATF750LVC-15XC

更新时间: 2024-11-23 23:33:07
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程逻辑器件光电二极管输入元件异步传输模式ATM时钟
页数 文件大小 规格书
14页 327K
描述
Electrically-Erasable Complex PLD

ATF750LVC-15XC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP24,.25
针数:24Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.75
其他特性:NO最大时钟频率:50 MHz
系统内可编程:NOJESD-30 代码:R-PDSO-G24
JESD-609代码:e0JTAG BST:NO
长度:7.8 mm湿度敏感等级:2
专用输入次数:11I/O 线路数量:10
宏单元数:10端子数量:24
最高工作温度:70 °C最低工作温度:
组织:11 DEDICATED INPUTS, 10 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP24,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
电源:3.3 V可编程逻辑类型:EE PLD
传播延迟:15 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Programmable Logic Devices
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

ATF750LVC-15XC 数据手册

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Features  
3.0V to 3.6V Operating Range  
Advanced, High-speed, Electrically-erasable Programmable Logic Device  
– Superset of 22V10  
– Enhanced Logic Flexibility  
– Architecturally Compatible with ATV750B and ATV750 Software and Hardware  
D- or T-type Flip-flop  
Product Term or Direct Input Pin Clocking  
15 ns Maximum Pin-to-pin Delay with 3V Operation  
Highest Density Programmable Logic Available in 24-pin Package  
– Advanced Electrically-erasable Technology  
– Reprogrammable  
– 100% Tested  
Increased Logic Flexibility  
High-speed  
Complex  
Programmable  
Logic Device  
– 42 Array Inputs, 20 Sum Terms and 20 Flip-flops  
Enhanced Output Logic Flexibility  
– All 20 Flip-flops Feed Back Internally  
– 10 Flip-flops are also Available as Outputs  
Programmable Pin-keeper Circuits  
Dual-in-line and Surface Mount Package in Standard Pinouts  
Commercial and Industrial Temperature Ranges  
20-year Data Retention  
ATF750LVC  
2000V ESD Protection  
1000 Erase/Write Cycles  
Block Diagram  
(OE PRODUCT TERMS)  
PROGRAMMABLE  
INTERCONNECT  
AND  
COMBINATORIAL  
LOGIC ARRAY  
12  
INPUT  
PINS  
LOGIC  
OPTION  
4 TO 8  
PRODUCT  
TERMS  
10  
I/O  
PINS  
OUTPUT  
OPTION  
(UP T0 20  
FLIP-FLOPS)  
(CLOCK PIN)  
Description  
The Atmel “750” architecture is twice as powerful as most other 24-pin programmable  
logic devices. Increased product terms, sum terms, flip-flops and output logic configu-  
rations translate into more usable gates. High-speed logic and uniform, predictable  
delays guarantee fast in-system performance. The ATF750LVC is a high-performance  
(continued)  
Pin Configurations  
Pin Name Function  
DIP/SOIC/TSSOP  
PLCC  
CLK/IN  
IN  
1
2
3
4
5
6
7
8
9
24 VCC  
23 I/O  
22 I/O  
21 I/O  
20 I/O  
19 I/O  
18 I/O  
17 I/O  
16 I/O  
15 I/O  
14 I/O  
13 IN  
CLK  
IN  
Clock  
IN  
IN  
IN  
5
6
7
8
9
25 I/O  
24 I/O  
23 I/O  
22 GND *  
21 I/O  
20 I/O  
19 I/O  
Logic Inputs  
Bi-directional Buffers  
Ground  
IN  
IN  
IN  
I/O  
IN  
GND *  
IN  
IN  
GND  
IN  
IN 10  
IN 11  
IN  
IN 10  
IN 11  
VCC  
3V Supply  
Note:  
For PLCC, pins 1, 8, 15, and 22  
can be left unconnected. For  
superior performance, connect  
VCC to pin 1 and GND to pins  
8, 15, and 22.  
GND 12  
Rev. 1447D–03/01  

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