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ATF530S20S PDF预览

ATF530S20S

更新时间： 2024-12-01 01:16:31
品牌 Logo 应用领域
POSEICO 开关
页数 文件大小 规格书
3页 92K
描述
FAST SWITCHING THYRISTOR

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中文翻译

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ATF530S20S 数据手册

 浏览型号ATF530S20S的Datasheet PDF文件第2页浏览型号ATF530S20S的Datasheet PDF文件第3页 
POSEICO  
POSEICO SPA  
POwer SEmiconductors Italian COrporation  
FAST SWITCHING THYRISTOR  
ATF530  
Repetitive voltage up to  
Mean on-state current  
Surge current  
2000  
1100  
V
A
15 kA  
50 µs  
TARGET SPECIFICATION  
apr 06 - ISSUE : 0  
Turn-off time  
Tj  
[
°
C
]  
Symbol  
Characteristic  
Conditions  
Value  
Unit  
BLOCKING  
V
V
V
I
RRM  
RSM  
DRM  
RRM  
DRM  
Repetitive peak reverse voltage  
Non-repetitive peak reverse voltage  
Repetitive peak off-state voltage  
Repetitive peak reverse current  
Repetitive peak off-state current  
125  
125  
125  
125  
125  
2000  
2100  
2000  
75  
V
V
V
V=VRRM  
V=VDRM  
mA  
mA  
I
75  
CONDUCTING  
I
I
I
T (AV)  
T (AV)  
TSM  
Mean on-state current  
180°sin, 50 Hz,Th=55°C, doubl e side cooled  
180°sin, 1 kHz,Tc=85°C, doub le side cooled  
sine wave, 10 ms  
1100  
900  
A
A
Mean on-state current  
Surge on-state current, non repetitive  
I² t  
125  
15  
kA  
I² t  
without reverse voltage  
1125 x1E3  
2,25  
A²s  
V
V
V
r
T
On-state voltage  
On-state current =  
2000 A  
25  
T(TO)  
T
Threshold voltage  
125  
1,30  
V
On-state slope resistance  
125 0,410  
mohm  
SWITCHING  
di/dt  
dv/dt  
td  
Critical rate of rise of on-state current, min  
Critical rate of rise of off-state voltage, min  
Gate controlled delay time, typical  
From 50% VDRM  
125  
125  
25  
800  
500  
1,5  
50  
A/µs  
V/µs  
µs  
Linear ramp up to 70% of VDRM  
VD=VDRM, gate source 20V, 20 ohm , tr=0.1 µs  
tq  
Circuit commutated turn-off time  
di/dt = 20  
A/µs, I I = 800  
A
125  
µs  
dV/dt = 200 V/µs , up to 75% VDRM  
Q rr  
I rr  
Reverse recovery charge  
Peak reverse recovery current  
Holding current, typical  
di/dt = 60  
VR = 50  
A/µs, I I = 1000  
A
125  
620  
300  
µC  
A
V
I
I
H
VD=5V, gate open circuit  
VD=5V, tp=30µs  
25  
25  
500  
mA  
mA  
L
Latching current, typical  
1000  
GATE  
GT  
V
I
Gate trigger voltage  
VD=6V  
25  
25  
125  
25  
25  
25  
25  
25  
3,0  
150  
0,3  
30  
10  
5
V
mA  
V
GT  
Gate trigger current  
VD=6V  
V
V
I
GD  
Non-trigger gate voltage, min.  
Peak gate voltage (forward)  
Peak gate current  
VD=VDRM  
FGM  
FGM  
RGM  
GM  
V
A
V
P
P
Peak gate voltage (reverse)  
Peak gate power dissipation  
Average gate power dissipation  
V
Pulse width 100 µs  
200  
3
W
W
G(AV)  
MOUNTING  
R
R
T
F
th(j-h)  
th(c-h)  
j
Thermal impedance, DC  
Junction to heatsink, double side cooled  
Case to heatsink, double side cooled  
26  
6
°C/kW  
°C/kW  
°C  
Thermal impedance, DC  
Operating junction temperature  
Mounting force  
-30 / 125  
14.0 / 17.0  
500  
kN  
Mass  
g
tq code  
D 10 µs C 12 µs B 15 µs A 20 µs L 25 µs  
M 30 µs N 35 µs P 40 µs R 45 µs S 50 µs  
T 60 µs U 70 µs W 80 µs X 100µs Y 150µs  
tq code  
ORDERING INFORMATION : ATF530 S 20 S  
VDRM&VRRM/100  
standard specification  
123

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