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ATF22LV10CZ-25XI PDF预览

ATF22LV10CZ-25XI

更新时间: 2024-11-26 22:50:15
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程逻辑器件
页数 文件大小 规格书
9页 226K
描述
High Performance E2 PLD

ATF22LV10CZ-25XI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:4.40 MM, PLASTIC, MO-153AD, TSSOP-24
针数:24Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.74
其他特性:10 MACROCELLS架构:PAL-TYPE
最大时钟频率:33.3 MHzJESD-30 代码:R-PDSO-G24
JESD-609代码:e0长度:7.8 mm
湿度敏感等级:2专用输入次数:11
I/O 线路数量:10输入次数:22
输出次数:10产品条款数:132
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C组织:11 DEDICATED INPUTS, 10 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP24,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240电源:3.3/5 V
可编程逻辑类型:FLASH PLD传播延迟:25 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Programmable Logic Devices最大供电电压:5.5 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

ATF22LV10CZ-25XI 数据手册

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Features  
3.0V to 5.5V Operating Range  
Advanced Low Voltage, Zero Power,  
Electrically Erasable Programmable Logic Device  
Edge-Sensing “Zero” Power  
Low Voltage Equivalent of ATF22V10CZ  
“Zero” Standby Power (25 µA Maximum)  
Ideal for Battery Powered Systems  
25 ns Maximum Propagation Delay  
CMOS and TTL Compatible Inputs and Outputs  
High  
Latch Feature Hold Inputs to Previous Logic States  
Advanced E2 Technology  
Performance  
E2 PLD  
Reprogrammable  
100% Tested  
High Reliability CMOS Process  
20 Year Data Retention  
100 Erase/Write Cycles  
2,000V ESD Protection  
200 mA Latchup Immunity  
ATF22LV10CZ  
Commercial and Industrial Temperature Ranges  
Dual-in-Line and Surface Mount Standard Pinouts  
Block Diagram  
ATF22LV10CZ  
TSSOP Top View  
Pin Configurations  
CLK/IN  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
IN  
Pin Name  
CLK  
IN  
Function  
IN  
IN  
2
3
Clock  
IN  
4
IN  
5
Logic Inputs  
Bidirectional Buffers  
(3 to 5.5V) Supply  
IN  
6
IN  
7
I/O  
IN  
8
IN  
9
VCC  
IN  
10  
11  
12  
IN  
GND  
DIP/SOIC  
PLCC  
Top view  
Note: For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For supe-  
rior performance, connect VCC to pin 1 and GND to pins 8, 15, and 22.  
Rev. 0779E/LV10CZ-E–05/98  

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