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ATC50

更新时间: 2024-11-21 20:10:31
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟微控制器外围集成电路
页数 文件大小 规格书
12页 90K
描述
RISC Microcontroller, 8-Bit, 33.3MHz, CMOS

ATC50 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknownECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:5.84
位大小:8最大时钟频率:33.3 MHz
认证状态:Not Qualified速度:33.3 MHz
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V技术:CMOS
uPs/uCs/外围集成电路类型:MICROCONTROLLER, RISCBase Number Matches:1

ATC50 数据手册

 浏览型号ATC50的Datasheet PDF文件第2页浏览型号ATC50的Datasheet PDF文件第3页浏览型号ATC50的Datasheet PDF文件第4页浏览型号ATC50的Datasheet PDF文件第5页浏览型号ATC50的Datasheet PDF文件第6页浏览型号ATC50的Datasheet PDF文件第7页 
Features  
Comprehensive Library of Standard Logic Cells  
ATC50 I/O Cells Designed to Operate with VDD = 3.3V ± 0.3V as Main Target Operating  
Conditions  
Introduction of IO35 Pad Library to Provide Interface to 5V Environment  
Oscillators and Phase Locked Loops for Stable Clock Sources  
Memory Cells Compiled to the Precise Requirements of the Design  
Basic Analog Library for ADC/DAC, OpAmp, Converters, and Voltage References  
Compatible with Atmel’s Extensive Range of Microcontroller, DSP, Standard Interface  
and Application Specific Cells  
High-Performance Analog Cells can be Developed on Request  
ATC50  
Description  
The Atmel ATC50 (AT55K) process is a proprietary 0.5 micron three-layer-metal  
CMOS process intended for use with a supply voltage of 3.3V ± 0.3V. The following  
table shows the range for which Atmel library cells have been characterized.  
ATC50  
Cell Based ASIC  
Summary  
Table 1. Recommended Operating Conditions  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
VDD3  
DC Supply Voltage  
Core and stan-  
dard I/Os  
3.0  
3.3  
3.6  
V
VDD5  
VI  
DC Supply  
5V interface I/Os  
VDD3  
0
5.0  
5.5  
VDD  
VDD  
+85  
V
V
DC Input Voltage  
DC Output Voltage  
VO  
0
V
TEMP  
Operating Free Air  
Temperature Range  
Industrial  
-40  
°C  
The Atmel cell libraries and megacell compilers have been designed in order to be  
compatible with each other. Simulation representations exist for three types of operat-  
ing conditions. They correspond to the following three characterization conditions:  
• MIN conditions:  
TJ = -55°C  
VDD (cell) = 3.60V  
Process = fast (industrial best case)  
• TYP conditions:  
TJ = +25°C  
VDD (cell) = 3.30V  
Process = typ (industrial typical case)  
• MAX conditions:  
TJ = +100°C  
V
DD (cell) = 2.85V  
Process = slow (industrial worst case)  
Delays to tristate are defined as delay to turn off (VGS < VT) of the driving devices.  
Output pad drain current corresponds to the output current of the pad when the output  
voltage is VOL or VOH. The output resistor of the pad and the voltage drop due to  
access resistors (in and out of the die) are taken into account. In order to have accu-  
rate timing estimates, all characterization has been run on electrical netlists extracted  
from the layout database.  
Rev. 0797DS–10/98  

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