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ATA5824C-PLQW PDF预览

ATA5824C-PLQW

更新时间: 2024-02-01 08:48:17
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
98页 1355K
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ATA5824C-PLQW 数据手册

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Features  
Full-duplex Operation Mode without Duplex Frequency Offset to Prevent the Relay  
Attack against Passive Entry Go (PEG) Systems  
High FSK Sensitivity: –105.5 dBm at 20 kBaud/–109 dBm at 2.4 kBaud (433.92 MHz)  
High ASK Sensitivity: –111.5 dBm at 10 kBaud/–116 dBm at 2.4 kBaud (100% ASK,  
Carrier Level 433.92 MHz)  
Low Supply Current: 10.5 mA in RX and TX Mode (3V/TX with 5 dBm/433.92 MHz)  
Data Rate 1 to 20 kBaud Manchester FSK, 1 to 10 kBaud Manchester  
ASK  
UHF ASK/FSK  
Transceiver  
ASK/FSK Receiver Uses a Low IF Architecture with High Selectivity,  
Blocking and Low Intermodulation (Typical 3 dB Blocking  
55.5 dBC at ±750 kHz/60.5 dBC at ±1.5 MHz and 67 dBC at ±10 MHz,  
System I1dBCP = –30 dBm/System IIP3 = –20 dBm)  
Wide Bandwidth AGC to Handle Large Outband Blockers above the System I1dBCP  
226 kHz IF (Intermediate Frequency) with 30 dB Image Rejection and 220 kHz System  
Bandwidth to Support TPM Transmitters using ATA5756/ATA5757 Transmitters with  
Standard Crystals  
ATA5823  
ATA5824  
Transmitter Uses Closed Loop FSK Modulation with Fractional-N Synthesizer with  
High PLL Bandwidth and an Excellent Isolation between PLL and PA  
Tolerances of XTAL Compensated by Fractional-N Synthesizer with 800 Hz RF  
Resolution  
Integrated RX/TX-Switch, Single-ended RF Input and Output  
RSSI (Received Signal Strength Indicator)  
Communication to Microcontroller with SPI Interface Working at 500 kBit/s Maximum  
Configurable Self Polling and RX/TX Protocol Handling with FIFO-RAM Buffering of  
Received and Transmitted Data  
1 Push Button Input and 1 Wake-up Input are Active in Power-down Mode  
Integrated XTAL Capacitors  
PA Efficiency: up to 38% (433.92 MHz/10 dBm/3V)  
Low In-band Sensitivity Change of Typically ±2.0 dB within ±75 kHz Center Frequency  
Change in the Complete Temperature and Supply Voltage Range  
Fully Integrated PLL with Low Phase Noise VCO, PLL Loop Filter and full support of  
multi-channel operation with arbitrary Channel distance due to Fractional-N  
Synthesizer  
Sophisticated Threshold Control and Quasi-peak Detector Circuit in the Data Slicer  
433.92 MHz, 868.3 MHz and 315 MHz without External VCO and PLL Components  
Efficient XTO Start-up Circuit (> –1.5 kWorst Case Start Impedance)  
Changing of Modulation Type ASK/FSK and Data Rate without Component Changes to  
Allow Different Modulation Schemes in TPM and RKE  
Minimal External Circuitry Requirements for Complete System Solution  
Adjustable Output Power: 0 to 10 dBm Adjusted and Stabilized with External Resistor,  
Programmable Output Power with 0.5dB Steps with Internal Resistor  
Clock and Interrupt Generation for Microcontroller  
ESD Protection at all Pins (±2.5 kV HBM, ±200V MM, ±500V FCDM)  
Supply Voltage Range: 2.15V to 3.6V or 4.4V to 5.25V  
Typical Power-down Current < 10 nA  
Temperature Range: –40°C to +105°C  
Small 7 mm × 7 mm QFN48 Package  
Rev. 4829C–RKE–09/05  

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