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AT91SAM7SE256-AU-999 PDF预览

AT91SAM7SE256-AU-999

更新时间: 2024-01-08 09:56:38
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器
页数 文件大小 规格书
47页 489K
描述
Microcontroller

AT91SAM7SE256-AU-999 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:,针数:128
Reach Compliance Code:unknown风险等级:5.83
Base Number Matches:1

AT91SAM7SE256-AU-999 数据手册

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Features  
Incorporates the ARM7TDMI® ARM® Thumb® Processor  
– High-performance 32-bit RISC Architecture  
– High-density 16-bit Instruction Set  
– Leader in MIPS/Watt  
– EmbeddedICEIn-circuit Emulation, Debug Communication Channel Support  
Internal High-speed Flash  
– 512 Kbytes, Organized in Two Contiguous Banks of 1024 Pages of 256 Bytes Dual  
Plane (AT91SAM7SE512)  
Product  
– 256 Kbytes (AT91SAM7SE256) Organized in One Bank of 1024 Pages of 256 Bytes  
Single Plane (AT91SAM7SE256)  
Description  
– 32 Kbytes (AT91SAM7SE32) Organized in One Bank of 256 Pages of 128 Bytes  
Single Plane (AT91SAM7SE32)  
– Single Cycle Access at Up to 30 MHz in Worst Case Conditions  
– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed  
– Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms  
– 10,000 Erase Cycles, 10-year Data Retention Capability, Sector Lock Capabilities,  
Flash Security Bit  
AT91SAM7SE512  
AT91SAM7SE256  
AT91SAM7SE32  
– Fast Flash Programming Interface for High Volume Production  
32 Kbytes (AT91SAM7SE512/256) or 8 Kbytes (AT91SAM7SE32) of Internal  
High-speed SRAM, Single-cycle Access at Maximum Speed  
One External Bus Interface (EBI)  
– Supports SDRAM, Static Memory, Glueless Connection to CompactFlash® and  
ECC-enabled NAND Flash  
Memory Controller (MC)  
Summary  
– Embedded Flash Controller  
– Memory Protection Unit  
– Abort Status and Misalignment Detection  
Reset Controller (RSTC)  
Preliminary  
– Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout  
Detector  
– Provides External Reset Signal Shaping and Reset Source Status  
Clock Generator (CKGR)  
– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and One PLL  
Power Management Controller (PMC)  
– Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and  
Idle Mode  
– Three Programmable External Clock Signals  
Advanced Interrupt Controller (AIC)  
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources  
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt  
Protected  
Debug Unit (DBGU)  
– Two-wire UART and Support for Debug Communication Channel interrupt,  
Programmable ICE Access Prevention  
NOTE: This is a summary document.  
The complete document is available on  
the Atmel website at www.atmel.com.  
– Mode for General Purpose Two-wire UART Serial Communication  
Periodic Interval Timer (PIT)  
– 20-bit Programmable Counter plus 12-bit Interval Counter  
Windowed Watchdog (WDT)  
6222ES–ATARM–15-Dec-09  
– 12-bit key-protected Programmable Counter  
 
 

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