Datasheet > AT90SC4816RS

AT90SC4816RS

更新时间： 2024-11-05 23:32:59

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
2页	31K
描述
AT90SC4816RS Summary [Updated 06/03. 2 Pages] Summary of the AT90SC4816RS giving the key features. a brief description and a block diagram.

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AT90SC4816RS 数据手册

Features

General

• High-performance, Low-power, Enhanced RISC Architecture

– 120 Powerful Instructions (Most Executed in a Single Clock Cycle)

• Low-power Idle and Power-down Modes

• Bond Pad Locations Conforming to ISO 7816-2

• ESD Protection to ± 6000V

• Operating Ranges: from 2.7V to 5.5V

• Compliant with GSM, 3GPP and EMV 2000 Specifications; PC Industry Compatible

• Available in Wafers, Modules and Industry-standard Packages

Secure

Microcontroller

for Smart Cards

Memory

• 48K Bytes of ROM Program Memory

• 16K Bytes of EEPROM, Including 64-byte OTP Area and 64-byte Bit-addressable Area

– 1 to 64-byte Program/Erase

– 1 ms Program, 1 ms Erase

– Typically More than 500,000 Write/Erase Cycles at a Temperature of 25^oC

– 10 Years Data Retention

• 1.5K Bytes RAM

AT90SC4816RS

Summary

Peripherals

• I/O Port

– Configurable to Support Communication Protocols Including ISO 7816-3

• 16-bit Timer

• Random Number Generator (FIPS 140-1)

• 2-level, 4-vector Interrupt Controller

Security

• Advanced Protection Against Physical Attack

• Environmental Protection Systems

• Voltage Monitor

• Frequency Monitor

• Secure Memory Management/Access Protection (Supervisor Mode)

Development Tools

• Voyager Emulation Platform (ATV2 Standard) to Support Software Development

• IAR Systems C-Spy Debugger

• Software Libraries and Application Notes

Description

The AT90SC4816RS is a low-power, high-performance, 8-bit microcontroller with

ROM and EEPROM memory, based on enhanced RISC architecture. The

AT90SC4816RS is code compatible with other members of the AT90SC family

(EEPROM drivers). Alternatively, on request, AT90SC4816RS can also be configured

to offer 100% compatibility with the AT90SC4816R.

By executing powerful instructions in a single clock cycle, the AT90SC4816RS

achieves throughputs close to 1 MIPS per MHz. Its Harvard architecture includes 32

general-purpose working registers directly connected to the ALU, allowing two inde-

pendent registers to be accessed in one single instruction executed in one clock

cycle.

Rev. 1591AS–SMIC-06/03

^{Note: This is a summary document. A complete document will be}1

available under NDA. For more information, please contact your

local Atmel sales office.

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