Features
• Compatible with MCS-51™ Products
• 4K Bytes of User Programmable QuickFlash™ Memory
• Fully Static Operation: 0 Hz to 24 MHz
• Three-Level Program Memory Lock
• 128 x 8-Bit Internal RAM
• 32 Programmable I/O Lines
• Two 16-Bit Timer/Counters
• Six Interrupt Sources
• Programmable Serial Channel
• Low Power Idle and Power Down Modes
8-Bit
Microcontroller
with 4K Bytes
QuickFlash™
Description
The AT87F51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K
bytes of QuickFlash Programmable Read Only Memory. The device is manufactured
using Atmel’s high density nonvolatile memory technology and is compatible with the
industry standard MCS-51™ instruction set and pinout. The on-chip QuickFlash
allows the program memory to be user programmed by a conventional nonvolatile
memory programmer. By combining a versatile 8-bit CPU with QuickFlash on a mono-
lithic chip, the Atmel AT87F51 is a powerful microcomputer which provides a highly
flexible and cost effective solution to many embedded control applications.
AT87F51
(continued)
PDIP
Pin Configurations
P 1 . 0
P 1 . 1
P 1 . 2
P 1 . 3
P 1 . 4
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
V C C
1
2
3
4
5
6
7
P 0 . 0 ( A D 0 )
P 0 . 1 ( A D 1 )
P 0 . 2 ( A D 2 )
P 0 . 3 ( A D 3 )
P 0 . 4 ( A D 4 )
P 0 . 5 ( A D 5 )
P 0 . 6 ( A D 6 )
P 0 . 7 ( A D 7 )
E A / V P P
P 1 . 5
P 1 . 6
P 1 . 7
R S T
8
9
( R X D ) P 3 . 0
( T X D ) P 3 . 1
( I N T 0 ) P 3 . 2
( I N T 1 ) P 3 . 3
( T 0 ) P 3 . 4
( T 1 ) P 3 . 5
( W R ) P 3 . 6
( R D ) P 3 . 7
X TA L 2
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
8TQFP
A L E / P R O G
P S E N
P 2 . 7 ( A 1 5 )
P 2 . 6 ( A 1 4 )
P 2 . 5 ( A 1 3 )
P 2 . 4 ( A 1 2 )
P 2 . 3 ( A 1 1 )
P 2 . 2 ( A 1 0 )
P 2 . 1 ( A 9 )
P 2 . 0 ( A 8 )
I N D E X
C O R N E R
4 4 4 2 4 0 3 8 3 6 3 4
4 3 4 1 3 9 3 7 3 5
X TA L 1
G N D
P 0 . 4 ( A D 4 )
P 0 . 5 ( A D 5 )
P 0 . 6 ( A D 6 )
P 0 . 7 ( A D 7 )
P 1 . 5
P 1 . 6
P 1 . 7
3 3
3 2
3 1
3 0
2 9
1
2
3
4
5
6
7
8
9
PLCC
R S T
( R X D ) P 3 . 0
N C
( T X D ) P 3 . 1
( I N T 0 ) P 3 . 2
( I N T 1 ) P 3 . 3
( T 0 ) P 3 . 4
( T 1 ) P 3 . 5
E A / V P P
N C
A L E / P R O G
P S E N
P 2 . 7 ( A 1 5 )
P 2 . 6 ( A 1 4 )
P 2 . 5 ( A 1 3 )
2 8
2 7
2 6
2 5
2 4
2 3
I N D E X
C O R N E R
1 0
1 1
6
4
2
4 4 4 2 4 0
1 9
1 8 2 0 2 2
1 3 1 5 1 7
2 1
5
3
1
4 3 4 1
3 9
P 1 . 5
P 0 . 4 ( A D 4 )
P 0 . 5 ( A D 5 )
P 0 . 6 ( A D 6 )
P 0 . 7 ( A D 7 )
E A / V P P
7
8
9
1 6
1 2 1 4
P 1 . 6
P 1 . 7
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
R S T
( R X D ) P 3 . 0
N C
( T X D ) P 3 . 1
( I N T 0 ) P 3 . 2
( I N T 1 ) P 3 . 3
( T 0 ) P 3 . 4
N C
A L E / P R O G
P S E N
P 2 . 7 ( A 1 5 )
P 2 . 6 ( A 1 4 )
P 2 . 5 ( A 1 3 )
( T 1 ) P 3 . 5
1 9 2 1 2 3 2 5 2 7
2 8
1 8 2 0 2 2 2 4 2 6
Rev. 1012A–02/98
1