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AT6010-2JC PDF预览

AT6010-2JC

更新时间: 2024-11-23 22:47:55
品牌 Logo 应用领域
爱特美尔 - ATMEL 现场可编程门阵列可编程逻辑静态存储器异步传输模式ATM时钟
页数 文件大小 规格书
28页 789K
描述
Coprocessor Field Programmable Gate Arrays

AT6010-2JC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:LCC
包装说明:PLASTIC, MS-018AF, LCC-84针数:84
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.89Is Samacsys:N
其他特性:SRAM BASED最大时钟频率:250 MHz
CLB-Max的组合延迟:2.4 nsJESD-30 代码:S-PQCC-J84
JESD-609代码:e0长度:29.3116 mm
湿度敏感等级:3可配置逻辑块数量:6400
等效关口数量:30000输入次数:64
逻辑单元数量:6400输出次数:64
端子数量:84最高工作温度:70 °C
最低工作温度:组织:6400 CLBS, 30000 GATES
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC84,1.2SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):225
电源:5 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Field Programmable Gate Arrays最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:29.3116 mmBase Number Matches:1

AT6010-2JC 数据手册

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Features  
High-performance  
– System Speeds > 100 MHz  
– Flip-flop Toggle Rates > 250 MHz  
– 1.2 ns/1.5 ns Input Delay  
– 3.0 ns/6.0 ns Output Delay  
Up to 204 User I/Os  
Thousands of Registers  
Cache Logic® Design  
Complete/Partial In-System Reconfiguration  
No Loss of Data or Machine State  
Adaptive Hardware  
Coprocessor  
Field  
Low Voltage and Standard Voltage Operation  
5.0 (VCC = 4.75V to 5.25V)  
3.3 (VCC = 3.0V to 3.6V)  
Programmable  
Gate Arrays  
Automatic Component Generators  
Reusable Custom Hard Macro Functions  
Very Low-power Consumption  
Standby Current of 500 µA/ 200 µA  
Typical Operating Current of 15 to 170 mA  
Programmable Clock Options  
AT6000(LV)  
Series  
Independently Controlled Column Clocks  
Independently Controlled Column Resets  
Clock Skew Less Than 1 ns Across Chip  
Independently Configurable I/O (PCI Compatible)  
TTL/CMOS Input Thresholds  
Open Collector/Tristate Outputs  
Programmable Slew-rate Control  
I/O Drive of 16 mA (combinable to 64 mA)  
Easy Migration to Atmel Gate Arrays for High Volume Production  
Description  
AT6000 Series SRAM-based Field Programmable Gate Arrays (FPGAs) are ideal for  
use as reconfigurable coprocessors and implementing compute-intensive logic.  
Supporting system speeds greater than 100 MHz and using a typical operating current  
of 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensive  
designs. These FPGAs are designed to implement Cache Logic®, which provides the  
user with the ability to implement adaptive hardware and perform hardware  
acceleration.  
The patented AT6000 Series architecture employs a symmetrical grid of small yet  
powerful cells connected to a flexible busing network. Independently controlled clocks  
and resets govern every column of cells. The array is surrounded by programmable  
I/O.  
(continued)  
AT6000 Series Field Programmable Gate Arrays  
Device  
AT6002  
6,000  
1,024  
1,024  
96  
AT6003  
9,000  
1,600  
1,600  
120  
AT6005  
15,000  
3,136  
AT6010  
30,000  
6,400  
Usable Gates  
Cells  
Registers (maximum)  
I/O (maximum)  
Typ. Operating Current (mA)  
Cell Rows x Columns  
3,136  
6,400  
108  
204  
Rev. 0264F10/99  
15 - 30  
32 x 32  
25 - 45  
40 x 40  
40 - 80  
56 x 56  
85 - 170  
80 x 80  

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