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AT49F002AT-55JU PDF预览

AT49F002AT-55JU

更新时间: 2024-11-05 04:05:55
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
20页 1098K
描述
Flash, 256KX8, 55ns, PQCC32, PLASTIC, MS-016AE, LCC-32

AT49F002AT-55JU 数据手册

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Features  
Single-voltage Operation  
– 5V Read  
– 5V Reprogramming  
Fast Read Access Time – 55 ns  
Internal Program Control and Timer  
Sector Architecture  
– One 16K Bytes Boot Block with Programming Lockout  
– Two 8K Bytes Parameter Blocks  
– Four Main Memory Blocks (One 32K Bytes, Three 64K Bytes)  
Fast Erase Cycle Time – 4 Seconds  
Byte-by-Byte Programming – 20 µs/Byte Typical  
Hardware Data Protection  
2-megabit  
(256K x 8)  
5-volt Only  
Flash Memory  
DATA Polling for End of Program Detection  
Low Power Dissipation  
– 30 mA Active Current  
– 100 µA CMOS Standby Current  
Typical 10,000 Write Cycles  
Green (Pb/Halide-free) Packaging Option  
AT49F002A  
AT49F002AN  
AT49F002AT  
AT49F002ANT  
1. Description  
The AT49F002A(N)(T) is a 5-volt only in-system reprogrammable Flash memory. Its  
2 megabits of memory is organized as 262,144 words by 8 bits. Manufactured with  
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to  
55 ns with power dissipation of just 165 mW over the industrial temperature range.  
Not Recommended  
When the device is deselected, the CMOS standby current is less than 100 µA. For  
the AT49F002AN(T) pin 1 for the PLCC package and pin 9 for the TSOP package are  
no connect pins.  
for New Design  
Contact Atmel to discuss  
the latest design in trends  
and options  
To allow for simple in-system reprogrammability, the AT49F002A(N)(T) does not  
require high input voltages for programming. Five-volt-only commands determine the  
read and programming operation of the device. Reading data out of the device is sim-  
ilar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus  
contention. Reprogramming the AT49F002A(N)(T) is performed by erasing a block of  
data and then programming on a byte-by-byte basis. The byte programming time is a  
fast 20 µs. The end of a program cycle can be optionally detected by the DATA polling  
feature. Once the end of a byte program cycle has been detected, a new access for a  
read or program can begin. The typical number of program and erase cycles is in  
excess of 10,000 cycles.  
The device is erased by executing the erase command sequence; the device inter-  
nally controls the erase operations. There are two 8K byte parameter block sections,  
four main memory blocks, and one boot block.  
The device has the capability to protect the data in the boot block; this feature is  
enabled by a command sequence. The 16K-byte boot block section includes a repro-  
gramming lock out feature to provide data integrity. The boot sector is designed to  
contain user secure code, and when the feature is enabled, the boot sector is pro-  
tected from being reprogrammed.  
3354G–FLASH–3/05  

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