Features
• Single 2.7V - 3.6V Supply
• Sequential Access, Parallel I/O Architecture
• Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 4096 Pages (264 Bytes/Page) Main Memory
• Two 264-Byte Data Buffers – Allows Receiving of Data while
Reprogramming of Non-Volatile Memory
• Internal Program and Control Timer
• Fast Page Program Time – 7 ms Typical
• 120 µs Typical Page to Buffer Transfer Time
• Low Power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
• 2 MHz Max Clock Frequency
• Hardware Data Protection Feature
8-Megabit
2.7-volt Only
Sequential
Access
• Synchronous Clocking (Two Modes)
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges
Parallel I/O
DataFlash®
Description
The AT45DB080 is a 2.7-volt only, sequential access, parallel interface Flash memory
suitable for in-system reprogramming. Its 8,650,752 bits of memory are organized as
4096 pages of 264-bytes each. In addition to the main memory, the AT45DB080 also
contains two data buffers of 264-bytes each. The buffers allow receiving of data while
a page in the main memory is being reprogrammed. Unlike conventional Flash memo-
ries that are accessed randomly with multiple address lines and a parallel interface,
AT45DB080
Preliminary
(continued)
Pin Configurations
Pin Name
Function
Chip Select
Clock
CS
CLK
I/O7-I/O0
Input/Output
Hardware Page
Write Protect Pin
WP
RESET
Chip Reset
Ready/Busy
TSOP Top View
Type 1
RDY/BUSY
SOIC
RDY/BUSY
RESET
WP
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
2
NC
GND
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
NC
3
NC
2
NC
4
I/O7
I/O6
I/O5
I/O4
VCC
GND
I/O3
I/O2
I/O1
I/O0
NC
NC
3
NC
NC
5
CS
4
WP
NC
6
CLK
DC
5
RESET
RDY/BUSY
NC
VCC
GND
NC
7
6
8
DC
7
9
NC
8
NC
NC
10
11
12
13
14
15
16
NC
9
NC
NC
I/O0
I/O1
I/O2
I/O3
GND
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
VCC
NC
CS
CLK
DC
NC
DC
NC
Rev. 1075B–06/98
Note:
SOIC pins 6 and 7 and TSOP pins 15 and 16 are DON’T CONNECT.
1