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AT34C02-W1.8-11 PDF预览

AT34C02-W1.8-11

更新时间： 2024-11-27 03:18:07
品牌 Logo 应用领域
爱特美尔 - ATMEL 存储内存集成电路异步传输模式ATM可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
21页 488K
描述
Two-wire Serial EEPROM with Permanent Software Write Protect

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中文翻译

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AT34C02-W1.8-11 技术参数

生命周期：Obsolete零件包装代码：DIE
包装说明：DIE,Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.51
风险等级：5.74最大时钟频率 (fCLK)：0.1 MHz
JESD-30 代码：X-XUUC-N内存密度：2048 bit
内存集成电路类型：EEPROM内存宽度：8
功能数量：1字数：256 words
字数代码：256工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256X8封装主体材料：UNSPECIFIED
封装代码：DIE封装形状：UNSPECIFIED
封装形式：UNCASED CHIP并行/串行：SERIAL
认证状态：Not Qualified串行总线类型：I2C
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：1.8 V
标称供电电压 (Vsup)：2.7 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：NO LEAD端子位置：UPPER
最长写入周期时间 (tWC)：5 msBase Number Matches：1

AT34C02-W1.8-11 数据手册

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Features  
• Permanent Software Write Protection for the First-half of the Array  
– Software Procedure to Verify Write Protect Status  
• Hardware Write Protection for the Entire Array  
• Low-voltage Operation  
– 1.8 (VCC = 1.8V to 5.5V)  
• Internally Organized 256 x 8  
• Two-wire Serial Interface  
• Schmitt Trigger, Filtered Inputs for Noise Suppression  
• Bidirectional Data Transfer Protocol  
• 100 kHz (1.8V) and 400 kHz (2.7V and 5.0V) Compatibility  
• 16-byte Page Write Modes  
• Partial Page Writes Are Allowed  
• Self-timed Write Cycle (5 ms max)  
Two-wire Serial  
EEPROM  
• High-reliability  
with Permanent  
Software Write  
Protect  
– Endurance: 1 Million Write Cycles  
– Data Retention: 100 Years  
• Automotive Grade Devices Available  
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 8-lead TSSOP, and 8-ball dBGA2  
Packages  
• Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers  
2K (256 x 8)  
Description  
The AT34C02 provides 2048 bits of serial electrically-erasable and programmable  
read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of  
the device incorporates a software write protection feature while hardware write pro-  
tection for the entire array is available via an external pin as well. Once the software  
write protection is enabled, by sending a special command to the device, it cannot be  
reversed. The hardware write protection is controlled with the WP pin and can be used  
to protect the entire array, whether or not the software write protection has been  
enabled. This allows the user to protect none, first-half, or all of the array depending  
on the application. The device is optimized for use in many industrial and commercial  
applications where low-power and low-voltage operations are essential. The AT34C02  
is available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 8-lead  
TSSOP and 8-ball dBGA2 packages and is accessed via a two-wire serial interface. In  
addition, it is available in 1.8V (1.8V to 5.5V) versions.  
AT34C02  
Note: Not recommended for new  
design; please refer to  
AT34CO2C datasheet.  
Table 1. Pin Configurations  
8-lead PDIP  
8-lead MAP  
Pin Name  
A0 - A2  
SDA  
Function  
A0  
A1  
1
2
3
4
8
7
6
5
VCC  
WP  
1
2
3
4
VCC  
WP  
8
7
6
5
A0  
A1  
Address Inputs  
Serial Data  
A2  
SCL  
SDA  
SCL  
SDA  
A2  
GND  
GND  
SCL  
Serial Clock Input  
Write Protect  
WP  
Bottom View  
8-ball dBGA2  
8-lead SOIC  
8-lead TSSOP  
8
7
6
5
1
2
3
4
VCC  
WP  
A0  
A0  
A1  
A2  
1
2
3
4
8
7
6
5
VCC  
WP  
A0  
A1  
1
2
3
4
8
7
6
5
VCC  
WP  
A1  
SCL  
SDA  
A2  
SCL  
SDA  
GND  
A2  
SCL  
SDA  
GND  
GND  
Bottom View  
Rev. 0958Q–SEEPR–1/07  
1234567...21

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