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AT29C257 PDF预览

AT29C257

更新时间: 2024-09-19 22:53:59
品牌 Logo 应用领域
爱特美尔 - ATMEL 闪存
页数 文件大小 规格书
12页 565K
描述
256K 32K x 8 5-volt Only CMOS Flash Memory

AT29C257 数据手册

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AT29C257  
Features  
Fast Read Access Time - 70 ns  
5-Volt-Only Reprogramming  
Page Program Operation  
Single Cycle Reprogram (Erase and Program)  
Internal Address and Data Latches for 64-Bytes  
Internal Program Control and Timer  
Hardware and Software Data Protection  
Fast Program Cycle Times  
Page (64-Byte) Program Time - 10 ms  
Chip Erase Time - 10 ms  
256K (32K x 8)  
5-volt Only  
CMOS Flash  
Memory  
DATA Polling for End of Program Detection  
Low Power Dissipation  
50 mA Active Current  
300 µA CMOS Standby Current  
Typical Endurance > 10,000 Cycles  
Single 5V ± 10% Supply  
CMOS and TTL Compatible Inputs and Outputs  
Pin-Compatible with AT29C010A and AT29C512 for Easy System Upgrades  
Description  
The AT29C257 is a 5-volt-only in-system Flash programmable and erasable read only  
memory (PEROM). Its 256K of memory is organized as 32,768 words by 8 bits. Manu-  
factured with Atmel’s advanced nonvolatile CMOS technology, the device offers ac-  
cess times to 70 ns with power dissipation of just 275 mW. When the device is dese-  
lected, the CMOS standby current is less than 300 µA. The device endurance is such  
that any sector can typically be written to in excess of 10,000 times.  
To allow for simple in-system reprogrammability, the AT29C257 does not require high  
input voltages for programming. Five-volt-only commands determine the operation of  
the device. Reading data out of the device is similar to reading from a static RAM.  
Reprogramming the AT29C257 is performed on a page basis; 64-bytes of data are  
loaded into the device and then simultaneously programmed. The contents of the  
entire device may be erased by using a 6-byte software code (although erasure before  
programming is not needed).  
AT29C257  
During a reprogram cycle, the address locations and 64-bytes of data are internally  
latched, freeing the address and data bus for other operations. Following the initiation  
of a program cycle, the device will automatically erase the page and then program the  
latched data using an internal control timer. The end of a program cycle can be de-  
tected by DATA polling of I/O7. Once the end of a program cycle has been detected  
a new access for a read, program or chip erase can begin.  
Pin Configurations  
PLCC Top View  
Pin Name Function  
A0 - A14  
CE  
Addresses  
Chip Enable  
Output Enable  
Write Enable  
OE  
WE  
I/O0 - I/O7 Data Inputs/Outputs  
NC  
DC  
No Connect  
Don’t Connect  
0012K  
4-105  

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