AT27C2048
Features
• Fast Read Access Time - 55 ns
• Low Power CMOS Operation
– 100 µA Maximum Standby
– 35 mA Maximum Active at 5 MHz
• JEDEC Standard Packages
– 40-Lead 600 mil PDIP
– 44-Lead PLCC
– 40-Lead TSOP (10 mm X 14 mm)
• Direct Upgrade from 512K bit and 1M bit
(AT27C516 and AT27C1024) EPROMs
• 5V ± 10% Power Supply
• High Reliability CMOS Technology
– 2,000V ESD Protection
2-Megabit
(128K x 16)
OTP EPROM
– 200 mA Latchup Immunity
• Rapid™ Programming Algorithm - 50 µs/word (typical)
• CMOS and TTL Compatible Inputs and Outputs
• Integrated Product Identification Code
• Commercial and Industrial Temperature Ranges
AT27C2048
Description
The AT27C2048 is a low-power, high performance 2,097,152-bit one-time program-
mable read only memory (OTP EPROM) organized 128K by 16 bits. It requires a sin-
gle 5V power supply in normal read mode operation. Any word can be accessed in
less than 55 ns, eliminating the need for speed-reducing WAIT states. The by-16
organization makes this part ideal for high-performance 16 and 32 bit microprocessor
systems.
(continued)
Pin Configurations
PDIP Top View
Pin Name Function
VPP
CE
1
2
3
4
5
6
7
8
9
40 VCC
39 PGM
38 A16
37 A15
36 A14
35 A13
34 A12
33 A11
32 A10
31 A9
30 GND
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 A2
22 A1
21 A0
O15
O14
O13
O12
O11
O10
O9
A0 - A16
O0 - O15
CE
Addresses
Outputs
Chip Enable
Output Enable
Program
O8 10
GND 11
O7 12
O6 13
O5 14
O4 15
O3 16
O2 17
O1 18
O0 19
OE 20
OE
PGM
NC
No Connect
Note:
Both GND pins must be con-
nected.
PLCC Top View
TSOP Top View
Type 1
A9
A10
A11
A12
A13
A14
A15
A16
PGM
VCC
VPP
CE
1
40
GND
A8
2
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
O12
O11
O10
7
8
9
39 A13
38 A12
37 A11
36 A10
35 A9
34 GND
33 NC
32 A8
31 A7
30 A6
29 A5
3
A7
4
A6
5
A5
O9 10
O8 11
GND 12
NC 13
O7 14
O6 15
O5 16
O4 17
6
A4
7
A3
8
A2
9
A1
10
11
12
13
14
15
16
17
18
19
20
A0
OE
O0
O1
O2
O3
O4
O5
O6
O7
GND
O15
O14
O13
O12
O11
O10
O9
0632B-A–06/97
O8
Note:
PLCC package pins 1 and 23
are DON’T CONNECT.
1