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AT25QF641-SUB-T PDF预览

AT25QF641-SUB-T

更新时间: 2024-11-07 02:52:03
品牌 Logo 应用领域
DIALOG /
页数 文件大小 规格书
74页 5991K
描述
64-Mbit, 2.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

AT25QF641-SUB-T 数据手册

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AT25QF641  
64-Mbit, 2.7V Minimum  
SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support  
Features  
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Single 2.7V - 3.6V Supply  
Serial Peripheral Interface (SPI) and Quad Peripheral Interface (QPI) Compatible  
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Supports SPI Modes 0 and 3  
Supports Dual Output Read and Quad I/O Program and Read  
Supports QPI Program and Read  
104 MHz* Maximum Operating Frequency  
Clock-to-Output (tV1) of 6 ns  
Up tp 52MB/S continuous data transfer rate  
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Quad Enabled (factory default setting: see Section 6-7)  
Full Chip Erase  
Flexible, Optimized Erase Architecture for Code and Data Storage Applications  
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0.6 ms Typical Page Program (256 Bytes) Time  
60 ms Typical 4-Kbyte Block Erase Time  
350 ms Typical 32-Kbyte Block Erase Time  
700 ms Typical 64-Kbyte Block Erase Time  
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Hardware Controlled Locking of Protected Blocks via WP Pin  
4K-bit secured One-Time Programmable Security Register  
Software and Hardware Write Protection  
Serial Flash Discoverable Parameters (SFDP) Register  
Flexible Programming  
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Byte/Page Program (1 to 256 Bytes)  
Dual or Quad Input Byte/Page Program (1 to 256 Bytes)  
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Erase/Program Suspend and Resume  
JEDEC Standard Manufacturer and Device ID Read Methodology  
Low Power Dissipation  
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2µA Deep Power-Down Current (Typical)  
10µA Standby current (Typical)  
5mA Active Read Current (Typical)  
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Endurance: 100,000 program/erase cycles (4KB, 32KB or 64KB blocks)  
Data Retention: 20 Years  
Industrial Temperature Range: -40°C to +85°C  
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options  
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8-lead SOIC (208-mil)  
8-pad DFN (6 x 5 x 0.6 mm)  
Die in Wafer Form  
DS-25QF641–127E–3/2018  

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