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AT25640A-10PA-2.7C PDF预览

AT25640A-10PA-2.7C

更新时间： 2024-11-25 03:15:35
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管
页数 文件大小 规格书
19页 401K
描述
EEPROM, 8KX8, Serial, CMOS, PDIP8, 0.300 INCH, PLASTIC, MS-001BA, DIP-8

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AT25640A-10PA-2.7C 数据手册

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Features  
• Serial Peripheral Interface (SPI) Compatible  
• Supports SPI Modes 0 (0,0) and 3 (1,1)  
– Data Sheet Describes Mode 0 Operation  
• Medium-voltage and Standard-voltage Operation  
– 5.0 (VCC = 4.5V to 5.5V)  
– 2.7 (VCC = 2.7V to 5.5V)  
• 5.0 MHz Clock Rate (5V)  
• 32-byte Page Mode  
• Block Write Protection  
– Protect 1/4, 1/2, or Entire Array  
• Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software  
Data Protection  
• Self-timed Write Cycle (2 ms [5V] typical)  
• High Reliability  
SPI Serial  
Automotive  
EEPROMs  
– Endurance: One Million Write Cycles  
– Data Retention: 100 Years  
8K (1024 x 8)  
16K (2048 x 8)  
32K (4096 x 8)  
64K (8192 x 8)  
• 8-lead PDIP and 8-lead JEDEC SOIC Packages  
Description  
The AT25080A/160A/320A/640A provides 8192/16384/32768/65536 bits of serial  
electrically-erasable programmable read-only memory (EEPROM) organized as  
1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many  
automotive applications where low-power and low-voltage operation are essential.  
The AT25080A/160A/320A/640A is available in space saving 8-lead PDIP and 8-lead  
JEDEC SOIC packages.  
AT25080A  
AT25160A  
AT25320A  
AT25640A  
The AT25080A/160A/320A/640A is enabled through the Chip Select pin (CS) and  
accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data  
Output (SO), and Serial Clock (SCK). All programming cycles are completely self-  
timed, and no separate erase cycle is required before write.  
Block write protection is enabled by programming the status register with one of four  
blocks of write protection. Separate program enable and program disable instructions  
are provided for additional data protection. Hardware data protection is provided via  
the WP pin to protect against inadvertent write attempts to the status register. The  
HOLD pin may be used to suspend any serial communication without resetting the  
serial sequence.  
8-lead PDIP  
Table 1. Pin Configuration  
Pin Name  
CS  
Function  
CS  
SO  
1
8
7
6
5
VCC  
HOLD  
SCK  
SI  
Chip Select  
2
3
4
SCK  
SI  
Serial Data Clock  
Serial Data Input  
Serial Data Output  
Ground  
WP  
GND  
SO  
GND  
VCC  
WP  
8-lead SOIC  
Power Supply  
Write Protect  
Suspends Serial Input  
No Connect  
CS  
SO  
1
8
7
6
5
VCC  
HOLD  
SCK  
SI  
2
3
4
HOLD  
NC  
WP  
GND  
DC  
Don’t Connect  
3401D–SEEPR–1/05  
1234567...19

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