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AT25640-10PA-5.0C PDF预览

AT25640-10PA-5.0C

更新时间： 2024-11-23 23:32:03
品牌 Logo 应用领域
其他 - ETC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
19页 257K
描述
SERIAL EEPROM|8KX8|CMOS|DIP|8PIN|PLASTIC

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中文翻译

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AT25640-10PA-5.0C 数据手册

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Features  
• Serial Peripheral Interface (SPI) Compatible  
• Supports SPI Modes 0 (0,0) and 3 (1,1)  
• Medium-voltage and Standard-voltage Operation  
– 5.0 (VCC = 4.5V to 5.5V)  
– 2.7 (VCC = 2.7V to 5.5V)  
• 3.0 MHz Clock Rate (5V)  
• 32-byte Page Mode  
• Block Write Protection  
– Protect 1/4, 1/2, or Entire Array  
• Write Protect (WP) Pin and Write Disable Instructions for  
both Hardware and Software Data Protection  
• Self-timed Write Cycle (5 ms Typical)  
• High-reliability  
– Endurance: One Million Write Cycles  
– Data Retention: 100 Years  
• 8-pin PDIP and 8-lead JEDEC SOIC Packages  
SPI Serial  
Automotive  
EEPROMs  
8K (1024 x 8)  
16K (2048 x 8)  
32K (4096 x 8)  
64K (8192 x 8)  
Description  
The AT25080/160/320/640 provides 8192/16384/32768/65536 bits of serial electri-  
cally-erasable programmable read only memory (EEPROM) organized as  
1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many  
automotive applications where low-power and low-voltage operation are essential.  
The AT25080/160/320/640 is available in space saving 8-pin PDIP and 8-lead JEDEC  
SOIC packages.  
The AT25080/160/320/640 is enabled through the Chip Select pin (CS) and accessed  
via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and  
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-  
rate ERASE cycle is required before WRITE.  
AT25080  
AT25160  
AT25320  
AT25640  
BLOCK WRITE protection is enabled by programming the status register with one of  
four blocks of write protection. Separate program enable and program disable instruc-  
tions are provided for additional data protection. Hardware data protection is provided  
via the WP pin to protect against inadvertent write attempts to the status register. The  
HOLD pin may be used to suspend any serial communication without resetting the  
serial sequence.  
Pin Configuration  
Pin Name  
Function  
8-pin PDIP  
8-lead SOIC  
CS  
Chip Select  
CS  
SO  
1
2
3
4
8
7
6
5
VCC  
HOLD  
SCK  
SI  
CS  
SO  
1
2
3
4
8
7
6
5
VCC  
HOLD  
SCK  
SI  
SCK  
SI  
Serial Data Clock  
Serial Data Input  
Serial Data Output  
Ground  
WP  
WP  
GND  
GND  
SO  
GND  
VCC  
WP  
Power Supply  
Write Protect  
Suspends Serial Input  
No Connect  
HOLD  
NC  
DC  
Don’t Connect  
Rev. 3260A–SEEPR–02/02  
1234567...19

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