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AT25256AN-10TQ-2.7 PDF预览

AT25256AN-10TQ-2.7

更新时间： 2024-02-26 16:58:25
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟光电二极管
页数 文件大小 规格书
18页 465K
描述
Memory IC, 32KX8, CMOS, PDSO8, TSSOP-8

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中文翻译

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AT25256AN-10TQ-2.7 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred包装说明：TSSOP,
Reach Compliance Code：compliant风险等级：5.68
其他特性：IT ALSO OPERATES AT 4.5 TO 5.5 V SUPPLY VOLTAGE最大时钟频率 (fCLK)：5 MHz
JESD-30 代码：R-PDSO-G8长度：4.4 mm
内存密度：262144 bit内存宽度：8
功能数量：1端子数量：8
字数：32768 words字数代码：32000
工作模式：SYNCHRONOUS最高工作温度：125 °C
最低工作温度：-40 °C组织：32KX8
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行：SERIAL峰值回流温度（摄氏度）：NOT SPECIFIED
座面最大高度：1.2 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3 mm
最长写入周期时间 (tWC)：5 msBase Number Matches：1

AT25256AN-10TQ-2.7 数据手册

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Features  
• Serial Peripheral Interface (SPI) Compatible  
• Supports SPI Modes 0 (0,0) and 3 (1,1)  
– Data Sheet Describes Mode 0 Operation  
• Medium-voltage and Standard-voltage Operation  
– 5.0 (VCC = 4.5V to 5.5V)  
– 2.7 (VCC = 2.7V to 5.5V)  
• 5 MHz Clock Rate  
• 64-byte Page Mode and Byte Write Operation  
• Block Write Protection  
– Protect 1/4, 1/2, or Entire Array  
• Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software  
Data Protection  
• Self-timed Write Cycle (5 ms max)  
• High Reliability  
SPI Serial  
Extended  
Temperature  
EEPROMs  
128K (16,384 x 8)  
256K (32,768 x 8)  
– Endurance: 100,000 Write Cycles  
– Data Retention: >100 Years  
• 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages  
Description  
The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable pro-  
grammable read-only memory (EEPROM) organized as 16,384/32,768 words of 8 bits  
each. The device is optimized for use in many industrial and automotive applications  
where low-power and low-voltage operation are essential. The devices are available in  
space-saving 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP packages.  
AT25128A  
AT25256A  
The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via a  
three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and  
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-  
rate erase cycle is required before write.  
Block write protection is enabled by programming the status register with top one-  
forth, top one-half, or entire array of write protection. Separate program enable and  
program disable instructions are provided for additional data protection. Hardware  
data protection is provided via the WP pin to protect against inadvertent write attempts  
to the status register. The HOLD pin may be used to suspend any serial communica-  
tion without resetting the serial sequence.  
8-Lead PDIP  
Table 1. Pin Configuration  
Pin Name  
CS  
Function  
1
2
3
4
8
7
6
5
CS  
SO  
WP  
VCC  
HOLD  
SCK  
SI  
Chip Select  
GND  
SCK  
SI  
Serial Data Clock  
Serial Data Input  
Serial Data Output  
Ground  
8-lead SOIC  
SO  
CS  
SO  
WP  
VCC  
1
2
3
4
8
7
6
5
GND  
VCC  
WP  
HOLD  
SCK  
SI  
Power Supply  
Write Protect  
Suspends Serial Input  
No Connect  
GND  
HOLD  
NC  
8-lead TSSOP  
1
2
3
4
8
7
6
5
CS  
SO  
WP  
VCC  
HOLD  
SCK  
SI  
DC  
Don't Connect  
5088A–SEEPR–9/04  
GND  
1234567...18

中文翻译

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