Features
• Low-voltage and Standard-voltage Operation
⎯ 1.8 (VCC = 1.8V to 5.5V)
• Internally Organized as 32,768 x 8
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5.0V, 2.7V, 2.5V), and 400 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 64-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Max)
Two-wire
Serial EEPROM
256K (32,768 x 8)
• High Reliability
⎯ Endurance: One Million Write Cycles
⎯ Data Retention: 40 Years
AT24C256C
• Lead-free/Halogen-free Devices Available
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, EIAJ SOIC, 8-lead Ultra Thin Small
Array Package (SAP), 8-lead TSSOP, and 8-ball dBGA2 Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
Description
The AT24C256C provides 262,144 bits of serial electrically erasable and
programmable read-only memory (EEPROM) organized as 32,768 words of 8 bits
each. The device’s cascadable feature allows up to eight devices to share a common
two-wire bus. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operation are essential. The devices
are available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra
Thin SAP, 8-lead TSSOP, and 8-ball dBGA2 packages. In addition, the entire family is
available in a 1.8V (1.8V to 5.5V) version.
Table 1.
Pin Configurations
Function
8-lead SOIC
8-lead PDIP
Pin Name
A0
A1
VCC
A0
A1
1
2
3
4
8
7
6
5
VCC
1
2
3
4
8
7
6
5
A0 – A2
SDA
Address Inputs
Serial Data
WP
WP
A2
SCL
SDA
A2
SCL
SDA
GND
GND
SCL
Serial Clock Input
8-ball dBGA2
8-lead TSSOP
WP
Write Protect
Ground
8
7
6
5
1
2
3
4
A0
A0
1
2
3
4
8
7
6
5
VCC
VCC
GND
A1
A2
WP
WP
SCL
SDA
A1
SCL
SDA
A2
GND
GND
Bottom View
8-lead Ultra-Thin SAP
8
7
6
5
1
2
3
4
VCC
WP
A0
A1
SCL
SDA
A2
GND
Bottom View
8568A–SEEPR–11/08