Datasheet > AT22V10L-30GM/883

AT22V10L-30GM/883

更新时间： 2024-02-11 21:10:43

品牌	Logo	应用领域
爱特美尔 - ATMEL		时钟输入元件可编程逻辑
页数	文件大小	规格书
11页	188K
描述
Programmable Logic Device

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技术参数
数据手册

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AT22V10L-30GM/883 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.82

AT22V10L-30GM/883 数据手册

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AT22V10/L

Features

High Speed Programmable Logic Device

•

15 ns Max Propagation Delay

5 V 10% Operation

Low Power CMOS Operation

•

Speed

Temp

"L"

Com./Mil. Com./Mil. Others

12/15 90/100 55

-15,-20

All

I (mA)

High Speed

CMOS and TTL Compatible Inputs and Outputs

10 µA Leakage Maximum

Reprogrammable - Tested 100% for Programmability

High Reliability CMOS Technology

2000 V ESD Protection

200 mA Latchup Immunity

Full Military, Commercial and Industrial Temperature Ranges

Dual-In-Line and Surface Mount Packages

•

UV Erasable

Programmable

Logic Device

•

Logic Diagram

OE PRODUCT TERMS

PROGRAMMABLE

INTERCONNECT

AND

LOGIC

OPTION

I/O PINS

OUTPUT

OPTION

INPUT PINS

COMBINATORIAL

LOGIC ARRAY

8 TO 16

PRODUCT

TERMS

(UP T0 10

FLIP-FLOPS)

Description

The AT22V10 and AT22V10L are CMOS high performance EPROM-based Programma-

ble Logic Devices (PLDs). Speeds down to 15 ns and power dissipation as low as 12 mA

are offered. All speed ranges are specified over the full 5 V 10% range. All pins offer a

low 10 µA leakage.

The AT22V10L provides the optimum low power CMOS PLD solution, with low DC power

(8 mA typical) and full CMOS output levels. The AT22V10L significantly reduces total

system power and enhances system reliability.

Full CMOS output levels help reduce power in many other system components.

The AT22V10 and AT22V10L incorporate a variable product term architecture. Each out-

put is allocated from eight to 16 product terms, which allows highly complex logic functions

to be realized.

Two additional product terms are included to provide synchronous preset and asynchro-

nous reset. These terms are common to all 10 registers. All registers are automatically

cleared upon power up.

grammed fuse patterns.

DIP/SOIC

PLCC

CLK/IN

IN IN

VCC

I/O

CLK/IN

Vcc

I/O

Pin Configurations

I/O

Pin Name

Function

I/O

CLK/IN

Clock and Logic Input

Logic Inputs

I/O

Bidirectional Buffers

No Internal Connection

+5 V Supply

I/O

GND

VCC

0023C

I/O

IN GND IN

1-97

12 3 4 5 6 7...11

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