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AT17N512-10SL PDF预览

AT17N512-10SL

更新时间: 2024-10-27 18:56:19
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟光电二极管内存集成电路
页数 文件大小 规格书
18页 295K
描述
Configuration Memory, 512KX1, Serial, CMOS, PDSO20, 0.300 INCH, PLASTIC, SOIC-20

AT17N512-10SL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.84最大时钟频率 (fCLK):15 MHz
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.8 mm内存密度:524288 bit
内存集成电路类型:CONFIGURATION MEMORY内存宽度:1
湿度敏感等级:2功能数量:1
端子数量:20字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX1封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:SERIAL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:2.64 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.5 mmBase Number Matches:1

AT17N512-10SL 数据手册

 浏览型号AT17N512-10SL的Datasheet PDF文件第2页浏览型号AT17N512-10SL的Datasheet PDF文件第3页浏览型号AT17N512-10SL的Datasheet PDF文件第4页浏览型号AT17N512-10SL的Datasheet PDF文件第5页浏览型号AT17N512-10SL的Datasheet PDF文件第6页浏览型号AT17N512-10SL的Datasheet PDF文件第7页 
Features  
EE Programmable 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and  
4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field  
Programmable Gate Arrays (FPGAs)  
Available as a 3.3V ( 10%) Commercial and Industrial Version  
Simple Interface to SRAM FPGAs  
Pin Compatible with Xilinx® XC17SXXXA and XC17SXXXXL PROMs  
Compatible with Xilinx Spartan®-II, Spartan-IIE and Spartan XL FPGAs in Master Serial  
Mode  
Very Low-power CMOS EEPROM Process  
Available in 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP Packages for a  
Specific Density  
Low-power Standby Mode  
FPGA  
Configuration  
Memory  
High-reliability  
– Endurance: Minimum 10 Write Cycles  
– Data Retention: 20 Years at 85°C  
Description  
AT17N256  
AT17N512  
AT17N010  
AT17N002  
AT17N040  
The AT17N series FPGA Configuration EEPROM (Configurators) provide an easy-to-  
use, cost-effective configuration memory for Field Programmable Gate Arrays. The  
AT17N series device is packaged in the 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and  
44-lead TQFP, see Table 1. The AT17N series Configurators uses a simple serial-  
access procedure to configure one or more FPGA devices.  
The AT17N series configurators can be programmed with industry-standard program-  
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable and  
factory programming.  
Table 1. AT17N Series Packages  
AT17N512/  
AT17N010  
3.3V  
Package  
AT17N256  
AT17N002  
AT17N040  
8-lead PDIP  
8-lead SOIC  
20-lead SOIC  
44-lead TQFP  
Yes  
Yes  
Yes  
Yes  
System Support  
Yes  
Yes  
Yes  
Yes  
3020C–CNFG–08/07  

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FPGA Configuration Flash Memory