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AT17N040-10TQC PDF预览

AT17N040-10TQC

更新时间: 2024-10-26 22:09:15
品牌 Logo 应用领域
爱特美尔 - ATMEL 存储
页数 文件大小 规格书
18页 202K
描述
FPGA Configuration Memory

AT17N040-10TQC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026ACB, TQFP-44
针数:44Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.92最大时钟频率 (fCLK):15 MHz
数据保留时间-最小值:20JESD-30 代码:S-PQFP-G44
JESD-609代码:e0长度:10 mm
内存密度:4194304 bit内存集成电路类型:CONFIGURATION MEMORY
内存宽度:1湿度敏感等级:3
功能数量:1端子数量:44
字数:4194304 words字数代码:4000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4MX1
封装主体材料:PLASTIC/EPOXY封装代码:TQFP
封装等效代码:TQFP44,.47SQ,32封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE并行/串行:SERIAL
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.00015 A子类别:EEPROMs
最大压摆率:0.005 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mmBase Number Matches:1

AT17N040-10TQC 数据手册

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Features  
EE Programmable 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and  
4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field  
Programmable Gate Arrays (FPGAs)  
Available as a 3.3V ( 10%) Commercial and Industrial Version  
Simple Interface to SRAM FPGAs  
Pin Compatible with Xilinx® XC17SXXXA and XC17SXXXXL PROMs  
Compatible with Xilinx Spartan®-II, Spartan-IIE and Spartan XL FPGAs in Master Serial  
Mode  
Very Low-power CMOS EEPROM Process  
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC  
Packages), 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP Packages for a  
Specific Density  
Low-power Standby Mode  
High-reliability  
FPGA  
Configuration  
Memory  
– Endurance: Minimum 10 Write Cycles  
– Data Retention: 20 Years at 85°C  
AT17N256  
AT17N512  
AT17N010  
AT17N002  
AT17N040  
Description  
The AT17N series FPGA Configuration EEPROM (Configurators) provide an easy-to-  
use, cost-effective configuration memory for Field Programmable Gate Arrays. The  
AT17N series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-lead  
SOIC and 44-lead TQFP, see Table 1. The AT17N series Configurators uses a simple  
serial-access procedure to configure one or more FPGA devices.  
The AT17N series configurators can be programmed with industry-standard program-  
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable and  
factory programming.  
Table 1. AT17N Series Packages  
3.3V  
AT17N512/  
AT17N010  
Package  
AT17N256  
AT17N002  
AT17N040  
System Support  
8-lead LAP  
8-lead PDIP  
8-lead SOIC  
20-lead SOIC  
44-lead TQFP  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Use 8-lead LAP(1)  
Use 8-lead LAP(1)  
Yes  
Yes  
Yes  
Yes  
Note:  
1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-  
lead SOIC package is not available for the AT17N512/010/002 devices, it is possi-  
ble to use an 8-lead LAP package instead.  
Rev. 3020A–CNFG–05/03  

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