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AT17LV512A-10JC PDF预览

AT17LV512A-10JC

更新时间: 2024-10-26 22:53:55
品牌 Logo 应用领域
爱特美尔 - ATMEL 存储
页数 文件大小 规格书
11页 137K
描述
FPGA Serial Configuration Memories

AT17LV512A-10JC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:LPCC
包装说明:QCCJ, LDCC20,.4SQ针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.51Factory Lead Time:1 week
风险等级:5.64其他特性:ALSO OPERATES AT 5V SUPPLY
最大时钟频率 (fCLK):15 MHzJESD-30 代码:S-PQCC-J20
JESD-609代码:e0长度:8.9662 mm
内存密度:524288 bit内存集成电路类型:CONFIGURATION MEMORY
内存宽度:1湿度敏感等级:2
功能数量:1端子数量:20
字数:524288 words字数代码:512000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX1
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:SERIAL
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified座面最大高度:4.572 mm
子类别:EEPROMs最大压摆率:0.005 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:8.9662 mm
写保护:HARDWAREBase Number Matches:1

AT17LV512A-10JC 数据手册

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Features  
Serial EEPROM Family for Configuring Altera FLEX 10K Devices  
Simple, Easy-to-use 4-pin Interface  
E2 Programmable 1M Bit Serial Memories Designed To Store Configuration Programs  
For Programmable Gate Arrays  
Cascadable To Support Additional Configurations or Future Higher-density Arrays  
Low-power CMOS EEPROM Process  
Programmable Reset Polarity  
Available in the Space-efficient Surface-mount PLCC Package  
In-System Programmable Via 2-Wire Bus  
Emulation of 24CXX Serial EPROMs  
Available in 3.3V ± 10% LV and 5V ± 5% C Versions  
FPGA Serial  
Configuration  
Memories  
Description  
The AT17C512/010A and AT17LV512/010A (AT17A Series) FPGA Configuration  
EEPROMs (Configurators) provide and easy-to-use, cost-effective configuration  
memory for programming Altera FLEX Field Programmable Gate Arrays, FPGA, (the  
“devices”). The AT17A Series is packaged in the popular 20-pin PLCC package. The  
AT17A Series family uses a simple serial-access procedure to configure one or more  
FPGA devices. The AT17A Series organization supplies enough memory to configure  
one or multiple smaller FPGAs. Using a special feature of the AT17A Series, the user  
can select the polarity of the reset function by programming an EEPROM byte. The  
AT17C/LV512/010A parts generate their own internal clock and can be used as a sys-  
tem “master” for loading the FPGA devices.  
AT17C512A  
AT17LV512A  
AT17C010A  
AT17LV010A  
The Atmel devices also supports a system friendly READY pin and a write protect  
mechanism. The READY pin is used to simplify system power-up considerations. The  
WP1 pin is used to protect part of the device memory during in-system programming.  
The AT17A Series can be programmed with industry standard programmers.  
Pin Configurations  
20-Pin PLCC  
DCLK  
WP1  
4
5
6
7
8
18 SER_EN  
17 NC  
NC  
16 NC  
NC  
15 READY  
14 NC  
RESET/OE  
Rev. 0974A–04/98  

AT17LV512A-10JC 替代型号

型号 品牌 替代类型 描述 数据表
AT17LV512A-10JU ATMEL

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