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AT17LV256-10PU PDF预览

AT17LV256-10PU

更新时间: 2024-11-18 06:38:15
品牌 Logo 应用领域
爱特美尔 - ATMEL 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
26页 617K
描述
FPGA Configuration EEPROM Memory

AT17LV256-10PU 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:DIP
包装说明:DIP, DIP8,.3针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:4.34
最长访问时间:80 ns其他特性:IT CAN OPERATES ON 4.75-5.25 RANGE SUPPLY VOLTAGE ALSO
最大时钟频率 (fCLK):10 MHzJESD-30 代码:R-PDIP-T8
JESD-609代码:e3长度:9.271 mm
内存密度:262144 bit内存集成电路类型:CONFIGURATION MEMORY
内存宽度:1湿度敏感等级:1
功能数量:1端子数量:8
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:256KX1
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP8,.3封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:SERIAL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified座面最大高度:5.334 mm
最大待机电流:0.0001 A子类别:EEPROMs
最大压摆率:0.005 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

AT17LV256-10PU 数据手册

 浏览型号AT17LV256-10PU的Datasheet PDF文件第2页浏览型号AT17LV256-10PU的Datasheet PDF文件第3页浏览型号AT17LV256-10PU的Datasheet PDF文件第4页浏览型号AT17LV256-10PU的Datasheet PDF文件第5页浏览型号AT17LV256-10PU的Datasheet PDF文件第6页浏览型号AT17LV256-10PU的Datasheet PDF文件第7页 
Features  
EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-,  
2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration  
Programs for Field Programmable Gate Arrays (FPGAs)  
Supports both 3.3V and 5.0V Operating Voltage Applications  
In-System Programmable (ISP) via Two-Wire Bus  
Simple Interface to SRAM FPGAs  
Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera® FLEX®, APEX™  
Devices, ORCA®, Xilinx® XC3000, XC4000, XC5200, Spartan®, Virtex® FPGAs  
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays  
Very Low-power CMOS EEPROM Process  
FPGA  
Configuration  
EEPROM  
Memory  
Programmable Reset Polarity  
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC  
Packages), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC and 44-lead TQFP  
Packages  
Emulation of Atmel’s AT24CXXX Serial EEPROMs  
Low-power Standby Mode  
High-reliability  
AT17LV65  
– Endurance: 100,000 Write Cycles  
– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for  
Commercial Parts (at 70°C)  
Green (Pb/Halide-free/RoHS Compliant) Package Options Available  
AT17LV128  
AT17LV256  
AT17LV512  
AT17LV010  
AT17LV002  
AT17LV040  
1. Description  
The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easy-  
to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The  
AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-  
lead PLCC, 20-lead SOIC and 44-lead TQFP, see Table 1-1. The AT17LV series  
Configurators uses a simple serial-access procedure to configure one or more FPGA  
devices. The user can select the polarity of the reset function by programming four  
EEPROM bytes. These devices also support a write-protection mechanism within its  
programming mode.  
3.3V and 5V  
System Support  
The AT17LV series configurators can be programmed with industry-standard pro-  
grammers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.  
2321I–CNFG–2/08  

AT17LV256-10PU 替代型号

型号 品牌 替代类型 描述 数据表
AT17LV256-10PI ATMEL

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