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AT17LV128-10JC PDF预览

AT17LV128-10JC

更新时间: 2024-11-17 22:37:15
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程只读存储器
页数 文件大小 规格书
10页 153K
描述
FPGA Configuration E2PROM

AT17LV128-10JC 数据手册

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Features  
E2 Programmable 65,536 x 1, 131,072 x 1, and 262,144 x 1 bit Serial Memories Designed  
To Store Configuration Programs For Programmable Gate Arrays  
Simple Interface to SRAM FPGAs Requires Only One User I/O Pin  
Compatible With AT6000 FPGAs, ATT3000 FPGA, EPF8000 FPGAs, ORCA FPGAs,  
XC2000, XC3000, XC4000, XC5000 FPGAs, MPA1000  
Cascadable To Support Additional Configurations or Future Higher-density Arrays  
(17C128 and 17C256 only)  
Low-power CMOS EEPROM Process  
Programmable Reset Polarity  
Available In the Space-efficient Plastic DIP or Surface-mount  
PLCC and SOIC Packages  
In-System Programmable Via 2-Wire Bus  
FPGA  
Configuration  
E2PROM  
Emulation of 24CXX Serial EPROMs  
Available in 3.3V ± 10% LV Version  
Description  
65K, 128K and 256K  
The AT17C65/128/256 and AT17LV65/128/256 (AT17 Series) FPGA Configuration  
EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration mem-  
ory for Field Programmable Gate Arrays. The AT17 Series is packaged in the 8-pin  
DIP and the popular 20-pin PLCC and SOIC. The AT17 Series family uses a simple  
serial-access procedure to configure one or more FPGA devices. The AT17 Series  
organization supplies enough memory to configure one or multiple smaller FPGAs.  
Using a special feature of the AT17 Series, the user can select the polarity of the reset  
function by programming a special EEPROM bit.  
AT17C65  
AT17C128  
AT17C256  
The AT17 Series can be programmed with industry standard programmers.  
Pin Configurations  
20-pin PLCC  
20-Pin SOIC  
8-Pin DIP  
0391E-A–5/97  

AT17LV128-10JC 替代型号

型号 品牌 替代类型 描述 数据表
AT17LV010-10JU MICROCHIP

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