Datasheet > AT17LV040

AT17LV040

更新时间： 2024-11-08 14:49:59

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
23页	669K
描述
Microchip 4-Mb FPGA configuration EEPROM provides easy-to-use, cost-effective configuration memory

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中文翻译

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数据手册

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AT17LV040 数据手册

AT17LV65⁽¹⁾, AT17LV128⁽¹⁾, AT17LV256,

AT17LV512, AT17LV010, AT17LV002, AT17LV040

FPGA Configuration EEPROM Memory

3.3V and 5.0V System Support

Note 1.

AT17LV65 and AT17LV128

are Not Recommended for

New Designs (NRND) and

are Replaced by AT17LV256.

DATASHEET

Features

 EE Programmable Serial Memories Designed to Store Configuration Programs

for Field Programmable Gate Arrays (FPGAs)

65,536 x 1-bit⁽¹⁾

131,072 x 1-bit⁽¹⁾

262,144 x 1-bit

524,288 x 1-bit

2,097,152 x 1-bit

4,194,304 x 1-bit

1,048,576 x 1-bit

 Supports both 3.3V and 5.0V Operating Voltage Applications

 In-System Programmable (ISP) via 2-wire Bus

 Simple Interface to SRAM FPGAs

 Compatible with the Atmel^®AT6000, AT40K and AT94K Devices, Altera^®

FLEX^®, APEX^™Devices, ORCA^®, Xilinx^®XC3000, XC4000, XC5200,

Spartan^®, Virtex^®FPGAs

 Cascadable Read-back to Support Additional Configurations or Higher-density

Arrays

 Very Low-power CMOS EEPROM Process

 Programmable Reset Polarity

 Available in 6mm x 6mm x 1mm 8-lead LAP (Pin-compatible with 8-lead SOIC

Package), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC and

44-lead TQFP Packages

 Emulation of the Atmel AT24CXXX Serial EEPROMs

 Low-power Standby Mode

 High-reliability

Endurance: 100,000 Write Cycles

Data Retention: 90 Years for Industrial Parts (at 85C)

 Green (Pb/Halide-free/RoHS Compliant) Package Options Available

Description

The AT17LV FPGA Configuration EEPROMs (Configurators) provide an easy-to-

use, cost-effective configuration memory solution for Field Programmable Gate

Arrays. The AT17LV devices are packaged in the 8-lead LAP, 8-lead PDIP, 8-lead

SOIC, 20-lead PLCC, 20-lead SOIC and 44-lead TQFP options(Table 1). The

AT17LV Configurators use a simple serial-access procedure to configure one or

more FPGA devices. The user can select the polarity of the reset function during

programming. These devices also support a write protection mechanism within its

programming mode.

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

12 3 4 5 6 7...23

中文翻译

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与AT17LV040相关器件

型号	品牌	获取价格	描述	数据表
AT17LV040-10AI	ATMEL	获取价格	Configuration Memory, 4MX1, Serial, CMOS, PQFP44, 1 MM HEIGHT, PLASTIC, MS-026ACB, TQFP-44
AT17LV040-10BJC	ATMEL	获取价格	FPGA Configuration EEPROM Memory
AT17LV040-10BJI	ATMEL	获取价格	FPGA Configuration EEPROM Memory
AT17LV040-10BJJ	ATMEL	获取价格	Configuration Memory, 4MX1, Serial, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44
AT17LV040-10BJL	ATMEL	获取价格	Configuration Memory, 4MX1, Serial, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44
AT17LV040-10CC	ATMEL	获取价格	FPGA Configuration EEPROM Memory
AT17LV040-10CI	ATMEL	获取价格	FPGA Configuration EEPROM Memory
AT17LV040-10JC	ATMEL	获取价格	FPGA Configuration EEPROM Memory
AT17LV040-10JI	ATMEL	获取价格	FPGA Configuration EEPROM Memory
AT17LV040-10NC	ATMEL	获取价格	FPGA Configuration EEPROM Memory

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