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AT17LV010-10DP-MQ PDF预览

AT17LV010-10DP-MQ

更新时间: 2024-11-18 06:38:15
品牌 Logo 应用领域
爱特美尔 - ATMEL 内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
11页 146K
描述
Space FPGA Configuration EEPROM

AT17LV010-10DP-MQ 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred零件包装代码:DFP
包装说明:DFP, FL28,.4针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.49
最大时钟频率 (fCLK):10 MHzJESD-30 代码:R-XDFP-F28
JESD-609代码:e0内存密度:1048576 bit
内存集成电路类型:CONFIGURATION MEMORY内存宽度:1
功能数量:1端子数量:28
字数:1048576 words字数代码:1000000
工作模式:SYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:1MX1
封装主体材料:UNSPECIFIED封装代码:DFP
封装等效代码:FL28,.4封装形状:RECTANGULAR
封装形式:FLATPACK并行/串行:SERIAL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified筛选级别:MIL-PRF-38535 Class Q
座面最大高度:3.3 mm子类别:EEPROMs
最大压摆率:0.01 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10.16 mm写保护:HARDWARE
Base Number Matches:1

AT17LV010-10DP-MQ 数据手册

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Features  
EE Programmable 1,048,576 x 1-bit Serial Memory Designed to Store Configuration  
Programs for Field Programmable Gate Arrays (FPGAs)  
Very Low-power CMOS EEPROM Process  
In-System Programmable (ISP) via Two-Wire Bus  
Simple Interface to SRAM FPGAs  
Compatible with AT40K Devices  
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays  
Programmable Reset Polarity  
Low-power Standby Mode  
High-reliability  
Space FPGA  
Configuration  
EEPROM  
– Endurance: 5,104 Read Cycles  
– Data Retention: 10 Years  
No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2  
Tested up to a Total Dose of (according to MIL STD 883 Method 1019)  
– 20 krads (Si) Read-only mode when Biased  
– 60 krads (Si) Read-only mode when Unbiased  
Operating Range: 3.0V to 3.6V, -55°C to +125°C  
Available in 400 mils Wide 28 Pins DIL Flat Pack  
AT17LV010-  
10DP  
Description  
The AT17LV010-10DP is a FPGA Configuration Serial EEPROM provides an easy-to-  
use, cost-effective configuration memory for Field Programmable Gate Arrays. It is  
packaged in the 28-pin 400 mils wide FP package. Configurator uses a simple serial-  
access procedure to configure one or more FPGA devices. The user can select the  
polarity of the reset function by programming four EEPROM bytes. The device also  
supports a write-protection mechanism within its programming mode.  
Rev. 4265C–AERO–05/05  

AT17LV010-10DP-MQ 替代型号

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AT17LV010-10DP-SV ATMEL

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